pocp.hier_info

简单的i/O接口的vhdl设计

|pocp
IRQ <= POC:inst1.IRQ
CLK => POC:inst1.CLK
CLK => printer:inst.clk
RESET => POC:inst1.RESET
RESET => printer:inst.reset
CS => POC:inst1.CS
RW => POC:inst1.RW
addr[0] => POC:inst1.ADDR[0]
addr[1] => POC:inst1.ADDR[1]
addr[2] => POC:inst1.ADDR[2]
data[0] => POC:inst1.DATA[0]
data[1] => POC:inst1.DATA[1]
data[2] => POC:inst1.DATA[2]
data[3] => POC:inst1.DATA[3]
data[4] => POC:inst1.DATA[4]
data[5] => POC:inst1.DATA[5]
data[6] => POC:inst1.DATA[6]
data[7] => POC:inst1.DATA[7]
pd[0] <= POC:inst1.PD[0]
pd[1] <= POC:inst1.PD[1]
pd[2] <= POC:inst1.PD[2]
pd[3] <= POC:inst1.PD[3]
pd[4] <= POC:inst1.PD[4]
pd[5] <= POC:inst1.PD[5]
pd[6] <= POC:inst1.PD[6]
pd[7] <= POC:inst1.PD[7]


|pocp|POC:inst1
CLK => BR[6].CLK
CLK => BR[5].CLK
CLK => BR[4].CLK
CLK => BR[3].CLK
CLK => BR[2].CLK
CLK => BR[1].CLK
CLK => BR[0].CLK
CLK => SR[7].CLK
CLK => SR[0].CLK
CLK => TR~reg0.CLK
CLK => PD[7]~reg0.CLK
CLK => PD[6]~reg0.CLK
CLK => PD[5]~reg0.CLK
CLK => PD[4]~reg0.CLK
CLK => PD[3]~reg0.CLK
CLK => PD[2]~reg0.CLK
CLK => PD[1]~reg0.CLK
CLK => PD[0]~reg0.CLK
CLK => IRQ~reg0.CLK
CLK => process0~2.CLK
CLK => process0~3.CLK
CLK => process0~5.CLK
CLK => process0~7.CLK
CLK => process0~9.CLK
CLK => process0~11.CLK
CLK => process0~13.CLK
CLK => process0~15.CLK
CLK => BR[7].CLK
RESET => TR~0.OUTPUTSELECT
RESET => SR~1.OUTPUTSELECT
RESET => PD[7]~reg0.ENA
RESET => PD[6]~reg0.ENA
RESET => PD[5]~reg0.ENA
RESET => PD[4]~reg0.ENA
RESET => PD[3]~reg0.ENA
RESET => PD[2]~reg0.ENA
RESET => PD[1]~reg0.ENA
RESET => PD[0]~reg0.ENA
RESET => process0~2.ENA
RESET => process0~3.ENA
RESET => process0~5.ENA
RESET => process0~7.ENA
RESET => process0~9.ENA
RESET => process0~11.ENA
RESET => process0~13.ENA
RESET => process0~15.ENA
CS => process0~1.IN1
RDY => TR~0.DATAA
RDY => SR~0.OUTPUTSELECT
RDY => process0~2.DATAIN
RDY => process0~3.DATAIN
RDY => process0~5.DATAIN
RDY => process0~7.DATAIN
RDY => process0~9.DATAIN
RDY => process0~11.DATAIN
RDY => process0~13.DATAIN
RDY => process0~15.DATAIN
RW => process0~0.IN1
ADDR[0] => Equal~0.IN5
ADDR[1] => Equal~0.IN4
ADDR[2] => Equal~0.IN3
DATA[0] => BR~7.DATAB
DATA[1] => BR~6.DATAB
DATA[2] => BR~5.DATAB
DATA[3] => BR~4.DATAB
DATA[4] => BR~3.DATAB
DATA[5] => BR~2.DATAB
DATA[6] => BR~1.DATAB
DATA[7] => BR~0.DATAB
TR <= TR~reg0.DB_MAX_OUTPUT_PORT_TYPE
IRQ <= IRQ~reg0.DB_MAX_OUTPUT_PORT_TYPE
PD[0] <= process0~17.DB_MAX_OUTPUT_PORT_TYPE
PD[1] <= process0~16.DB_MAX_OUTPUT_PORT_TYPE
PD[2] <= process0~14.DB_MAX_OUTPUT_PORT_TYPE
PD[3] <= process0~12.DB_MAX_OUTPUT_PORT_TYPE
PD[4] <= process0~10.DB_MAX_OUTPUT_PORT_TYPE
PD[5] <= process0~8.DB_MAX_OUTPUT_PORT_TYPE
PD[6] <= process0~6.DB_MAX_OUTPUT_PORT_TYPE
PD[7] <= process0~4.DB_MAX_OUTPUT_PORT_TYPE


|pocp|printer:inst
rdy <= 2.DB_MAX_OUTPUT_PORT_TYPE
clk => 3.IN0
tr => 1.IN0
reset => 2.IN1


|pocp|printer:inst|74193:7
BON <= 28.DB_MAX_OUTPUT_PORT_TYPE
CLR => 44.IN0
LDN => 43.IN0
B => 53.IN2
A => 52.IN2
DN => 90.IN0
UP => 89.IN0
C => 54.IN2
D => 55.IN2
CON <= 27.DB_MAX_OUTPUT_PORT_TYPE
QD <= 23.DB_MAX_OUTPUT_PORT_TYPE
QC <= 24.DB_MAX_OUTPUT_PORT_TYPE
QB <= 25.DB_MAX_OUTPUT_PORT_TYPE
QA <= 26.DB_MAX_OUTPUT_PORT_TYPE