pocp.fnsim.qmsg

简单的i/O接口的vhdl设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Mar 15 17:45:21 2009 " "Info: Processing started: Sun Mar 15 17:45:21 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pocp -c pocp --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pocp -c pocp --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "POC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file POC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 POC-BEHAV " "Info: Found design unit 1: POC-BEHAV" {  } { { "POC.vhd" "" { Text "E:/pocp/POC.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 POC " "Info: Found entity 1: POC" {  } { { "POC.vhd" "" { Text "E:/pocp/POC.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "printer.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file printer.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 printer " "Info: Found entity 1: printer" {  } { { "printer.bdf" "" { Schematic "E:/pocp/printer.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pocp.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file pocp.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 pocp " "Info: Found entity 1: pocp" {  } { { "pocp.bdf" "" { Schematic "E:/pocp/pocp.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pocp " "Info: Elaborating entity \"pocp\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "POC POC:inst1 " "Info: Elaborating entity \"POC\" for hierarchy \"POC:inst1\"" {  } { { "pocp.bdf" "inst1" { Schematic "E:/pocp/pocp.bdf" { { 144 624 776 304 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "printer printer:inst " "Info: Elaborating entity \"printer\" for hierarchy \"printer:inst\"" {  } { { "pocp.bdf" "inst" { Schematic "E:/pocp/pocp.bdf" { { 144 280 376 240 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/others/maxplus2/74193.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/74193.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74193 " "Info: Found entity 1: 74193" {  } { { "74193.bdf" "" { Schematic "c:/altera/quartus51/libraries/others/maxplus2/74193.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74193 printer:inst\|74193:7 " "Info: Elaborating entity \"74193\" for hierarchy \"printer:inst\|74193:7\"" {  } { { "printer.bdf" "7" { Schematic "E:/pocp/printer.bdf" { { 224 760 880 384 "7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "POC:inst1\|SR\[0\] High " "Info: Power-up level of register \"POC:inst1\|SR\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "POC.vhd" "" { Text "E:/pocp/POC.vhd" 18 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "POC:inst1\|SR\[0\] data_in VCC " "Warning: Reduced register \"POC:inst1\|SR\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "POC.vhd" "" { Text "E:/pocp/POC.vhd" 18 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 15 17:45:23 2009 " "Info: Processing ended: Sun Mar 15 17:45:23 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}