pocp.fit.rpt

简单的i/O接口的vhdl设计

; 6                                          ; 0                           ;
; 7                                          ; 0                           ;
; 8                                          ; 1                           ;
; 9                                          ; 0                           ;
; 10                                         ; 1                           ;
+--------------------------------------------+-----------------------------+


+------------------------------------------------------------------+
; LAB-wide Signals                                                 ;
+------------------------------------+-----------------------------+
; LAB-wide Signals  (Average = 1.29) ; Number of LABs  (Total = 7) ;
+------------------------------------+-----------------------------+
; 1 Async. clear                     ; 2                           ;
; 1 Clock                            ; 5                           ;
; 1 Clock enable                     ; 2                           ;
+------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Signals Sourced                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced  (Average = 4.43) ; Number of LABs  (Total = 7) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 2                           ;
; 2                                           ; 1                           ;
; 3                                           ; 0                           ;
; 4                                           ; 1                           ;
; 5                                           ; 1                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 1                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out                                                       ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out  (Average = 3.29) ; Number of LABs  (Total = 7) ;
+-------------------------------------------------+-----------------------------+
; 0                                               ; 0                           ;
; 1                                               ; 2                           ;
; 2                                               ; 2                           ;
; 3                                               ; 0                           ;
; 4                                               ; 0                           ;
; 5                                               ; 1                           ;
; 6                                               ; 2                           ;
+-------------------------------------------------+-----------------------------+


+---------------------------------------------------------------------------+
; LAB Distinct Inputs                                                       ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs  (Average = 5.71) ; Number of LABs  (Total = 7) ;
+---------------------------------------------+-----------------------------+
; 0                                           ; 0                           ;
; 1                                           ; 0                           ;
; 2                                           ; 2                           ;
; 3                                           ; 1                           ;
; 4                                           ; 0                           ;
; 5                                           ; 1                           ;
; 6                                           ; 1                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 1                           ;
; 11                                          ; 0                           ;
; 12                                          ; 1                           ;
+---------------------------------------------+-----------------------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 15 17:45:05 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pocp -c pocp
Info: Automatically selected device EPM240T100C3 for design pocp
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T100C3 is compatible
Info: No exact pin location assignment(s) for 24 pins of 24 total pins
    Info: Pin IRQ not assigned to an exact location on the device
    Info: Pin pd[7] not assigned to an exact location on the device
    Info: Pin pd[6] not assigned to an exact location on the device
    Info: Pin pd[5] not assigned to an exact location on the device
    Info: Pin pd[4] not assigned to an exact location on the device
    Info: Pin pd[3] not assigned to an exact location on the device
    Info: Pin pd[2] not assigned to an exact location on the device
    Info: Pin pd[1] not assigned to an exact location on the device
    Info: Pin pd[0] not assigned to an exact location on the device
    Info: Pin CLK not assigned to an exact location on the device
    Info: Pin addr[2] not assigned to an exact location on the device
    Info: Pin addr[0] not assigned to an exact location on the device
    Info: Pin CS not assigned to an exact location on the device
    Info: Pin RW not assigned to an exact location on the device
    Info: Pin addr[1] not assigned to an exact location on the device
    Info: Pin RESET not assigned to an exact location on the device
    Info: Pin data[7] not assigned to an exact location on the device
    Info: Pin data[6] not assigned to an exact location on the device
    Info: Pin data[5] not assigned to an exact location on the device
    Info: Pin data[4] not assigned to an exact location on the device
    Info: Pin data[3] not assigned to an exact location on the device
    Info: Pin data[2] not assigned to an exact location on the device
    Info: Pin data[1] not assigned to an exact location on the device
    Info: Pin data[0] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "CLK" to use Global clock in PIN 14
    Info: Destination "printer:inst|74193:7|28~14" may be non-global or may not use global clock
    Info: Destination "printer:inst|3" may be non-global or may not use global clock
    Info: Destination "printer:inst|74193:7|6~11" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "POC:inst1|TR" to use Global clock
    Info: Destination "printer:inst|4" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 23 (unused VREF, 3.30 VCCIO, 14 input, 9 output, 0 bidirectional)
        Info: I/O standards used: LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used --  37 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 5.740 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X3_Y2; Fanout = 7; REG Node = 'printer:inst|74193:7|23'
    Info: 2: + IC(0.000 ns) + CELL(4.820 ns) = 4.820 ns; Loc. = LAB_X3_Y2; Fanout = 3; COMB LOOP Node = 'printer:inst|74193:7|28~15'
        Info: Loc. = LAB_X2_Y2; Node "printer:inst|2"
        Info: Loc. = LAB_X3_Y2; Node "printer:inst|74193:7|28~15"
        Info: Loc. = LAB_X3_Y2; Node "printer:inst|4"
        Info: Loc. = LAB_X3_Y2; Node "printer:inst|74193:7|28~14"
    Info: 3: + IC(0.418 ns) + CELL(0.502 ns) = 5.740 ns; Loc. = LAB_X3_Y2; Fanout = 9; REG Node = 'POC:inst1|TR'
    Info: Total cell delay = 5.322 ns ( 92.72 % )
    Info: Total interconnect delay = 0.418 ns ( 7.28 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 3% of the available device resources. Peak interconnect usage is 3%
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and routability requirements required full optimization.
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
    Info: Processing ended: Sun Mar 15 17:45:06 2009
    Info: Elapsed time: 00:00:02