pocp.map.eqn

简单的i/O接口的vhdl设计

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--C1_IRQ is POC:inst1|IRQ
--operation mode is normal

C1_IRQ_lut_out = C1_SR[7];
C1_IRQ = DFFEAS(C1_IRQ_lut_out, CLK, VCC, , , , , , );


--C1_SR[7] is POC:inst1|SR[7]
--operation mode is normal

C1_SR[7]_lut_out = C1L28 # addr[1] # !B1_2;
C1_SR[7] = DFFEAS(C1_SR[7]_lut_out, CLK, VCC, , , , , , );


--C1L26Q is POC:inst1|PD[7]~reg0
--operation mode is normal

C1L26Q_lut_out = C1L10;
C1L26Q = DFFEAS(C1L26Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L27Q is POC:inst1|process0~2
--operation mode is normal

C1L27Q_lut_out = !B1_2;
C1L27Q = DFFEAS(C1L27Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L25Q is POC:inst1|PD[6]~reg0
--operation mode is normal

C1L25Q_lut_out = C1L11;
C1L25Q = DFFEAS(C1L25Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L24Q is POC:inst1|PD[5]~reg0
--operation mode is normal

C1L24Q_lut_out = C1L12;
C1L24Q = DFFEAS(C1L24Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L23Q is POC:inst1|PD[4]~reg0
--operation mode is normal

C1L23Q_lut_out = C1L13;
C1L23Q = DFFEAS(C1L23Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L22Q is POC:inst1|PD[3]~reg0
--operation mode is normal

C1L22Q_lut_out = C1L14;
C1L22Q = DFFEAS(C1L22Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L21Q is POC:inst1|PD[2]~reg0
--operation mode is normal

C1L21Q_lut_out = C1L15;
C1L21Q = DFFEAS(C1L21Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L20Q is POC:inst1|PD[1]~reg0
--operation mode is normal

C1L20Q_lut_out = C1L16;
C1L20Q = DFFEAS(C1L20Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L19Q is POC:inst1|PD[0]~reg0
--operation mode is normal

C1L19Q_lut_out = C1L17;
C1L19Q = DFFEAS(C1L19Q_lut_out, CLK, VCC, , RESET, , , , );


--C1L28 is POC:inst1|process0~57
--operation mode is normal

C1L28 = addr[2] # addr[0] # !RW # !CS;


--D1_23 is printer:inst|74193:7|23
--operation mode is normal

D1_23_lut_out = !D1_23;
D1_23 = DFFEAS(D1_23_lut_out, D1L7, !C1_TR, , , , , , );


--D1_24 is printer:inst|74193:7|24
--operation mode is normal

D1_24_lut_out = !D1_24;
D1_24 = DFFEAS(D1_24_lut_out, D1L6, !C1_TR, , , , , , );


--D1_26 is printer:inst|74193:7|26
--operation mode is normal

D1_26_lut_out = !D1_26;
D1_26 = DFFEAS(D1_26_lut_out, B1_3, !C1_TR, , , , , , );


--D1_25 is printer:inst|74193:7|25
--operation mode is normal

D1_25_lut_out = !D1_25;
D1_25 = DFFEAS(D1_25_lut_out, D1L1, !C1_TR, , , , , , );


--D1L6 is printer:inst|74193:7|28~14
--operation mode is normal

D1L6 = D1_25 # B1_4 # !D1_26 # !CLK;


--D1L7 is printer:inst|74193:7|28~15
--operation mode is normal

D1L7 = D1L6 # !D1_24;


--B1_2 is printer:inst|2
--operation mode is normal

B1_2 = RESET & !B1_4 & (D1_23 # D1L7);


--C1_BR[7] is POC:inst1|BR[7]
--operation mode is normal

C1_BR[7]_lut_out = C1L10;
C1_BR[7] = DFFEAS(C1_BR[7]_lut_out, CLK, VCC, , , , , , );


--C1L10 is POC:inst1|BR~448
--operation mode is normal

C1L10 = C1L28 & C1_BR[7] # !C1L28 & (addr[1] & C1_BR[7] # !addr[1] & (data[7]));


--C1_BR[6] is POC:inst1|BR[6]
--operation mode is normal

C1_BR[6]_lut_out = C1L11;
C1_BR[6] = DFFEAS(C1_BR[6]_lut_out, CLK, VCC, , , , , , );


--C1L11 is POC:inst1|BR~449
--operation mode is normal

C1L11 = C1L28 & C1_BR[6] # !C1L28 & (addr[1] & C1_BR[6] # !addr[1] & (data[6]));


--C1_BR[5] is POC:inst1|BR[5]
--operation mode is normal

C1_BR[5]_lut_out = C1L12;
C1_BR[5] = DFFEAS(C1_BR[5]_lut_out, CLK, VCC, , , , , , );


--C1L12 is POC:inst1|BR~450
--operation mode is normal

C1L12 = C1L28 & C1_BR[5] # !C1L28 & (addr[1] & C1_BR[5] # !addr[1] & (data[5]));


--C1_BR[4] is POC:inst1|BR[4]
--operation mode is normal

C1_BR[4]_lut_out = C1L13;
C1_BR[4] = DFFEAS(C1_BR[4]_lut_out, CLK, VCC, , , , , , );


--C1L13 is POC:inst1|BR~451
--operation mode is normal

C1L13 = C1L28 & C1_BR[4] # !C1L28 & (addr[1] & C1_BR[4] # !addr[1] & (data[4]));


--C1_BR[3] is POC:inst1|BR[3]
--operation mode is normal

C1_BR[3]_lut_out = C1L14;
C1_BR[3] = DFFEAS(C1_BR[3]_lut_out, CLK, VCC, , , , , , );


--C1L14 is POC:inst1|BR~452
--operation mode is normal

C1L14 = C1L28 & C1_BR[3] # !C1L28 & (addr[1] & C1_BR[3] # !addr[1] & (data[3]));


--C1_BR[2] is POC:inst1|BR[2]
--operation mode is normal

C1_BR[2]_lut_out = C1L15;
C1_BR[2] = DFFEAS(C1_BR[2]_lut_out, CLK, VCC, , , , , , );


--C1L15 is POC:inst1|BR~453
--operation mode is normal

C1L15 = C1L28 & C1_BR[2] # !C1L28 & (addr[1] & C1_BR[2] # !addr[1] & (data[2]));


--C1_BR[1] is POC:inst1|BR[1]
--operation mode is normal

C1_BR[1]_lut_out = C1L16;
C1_BR[1] = DFFEAS(C1_BR[1]_lut_out, CLK, VCC, , , , , , );


--C1L16 is POC:inst1|BR~454
--operation mode is normal

C1L16 = C1L28 & C1_BR[1] # !C1L28 & (addr[1] & C1_BR[1] # !addr[1] & (data[1]));


--C1_BR[0] is POC:inst1|BR[0]
--operation mode is normal

C1_BR[0]_lut_out = C1L17;
C1_BR[0] = DFFEAS(C1_BR[0]_lut_out, CLK, VCC, , , , , , );


--C1L17 is POC:inst1|BR~455
--operation mode is normal

C1L17 = C1L28 & C1_BR[0] # !C1L28 & (addr[1] & C1_BR[0] # !addr[1] & (data[0]));


--C1_TR is POC:inst1|TR
--operation mode is normal

C1_TR_lut_out = RESET & (B1_4 # !D1L7 & !D1_23);
C1_TR = DFFEAS(C1_TR_lut_out, CLK, VCC, , , , , , );


--B1_3 is printer:inst|3
--operation mode is normal

B1_3 = B1_4 # !CLK;


--D1L1 is printer:inst|74193:7|6~11
--operation mode is normal

D1L1 = B1_4 # !D1_26 # !CLK;


--B1_4 is printer:inst|4
--operation mode is normal

B1_4 = !B1_2 & !C1_TR;


--CLK is CLK
--operation mode is input

CLK = INPUT();


--addr[2] is addr[2]
--operation mode is input

addr[2] = INPUT();


--addr[0] is addr[0]
--operation mode is input

addr[0] = INPUT();


--CS is CS
--operation mode is input

CS = INPUT();


--RW is RW
--operation mode is input

RW = INPUT();


--addr[1] is addr[1]
--operation mode is input

addr[1] = INPUT();


--RESET is RESET
--operation mode is input

RESET = INPUT();


--data[7] is data[7]
--operation mode is input

data[7] = INPUT();


--data[6] is data[6]
--operation mode is input

data[6] = INPUT();


--data[5] is data[5]
--operation mode is input

data[5] = INPUT();


--data[4] is data[4]
--operation mode is input

data[4] = INPUT();


--data[3] is data[3]
--operation mode is input

data[3] = INPUT();


--data[2] is data[2]
--operation mode is input

data[2] = INPUT();


--data[1] is data[1]
--operation mode is input

data[1] = INPUT();


--data[0] is data[0]
--operation mode is input

data[0] = INPUT();


--IRQ is IRQ
--operation mode is output

IRQ = OUTPUT(C1_IRQ);


--pd[7] is pd[7]
--operation mode is output

pd[7]_tri_out = TRI(C1L26Q, C1L27Q);
pd[7] = OUTPUT(pd[7]_tri_out);


--pd[6] is pd[6]
--operation mode is output

pd[6]_tri_out = TRI(C1L25Q, C1L27Q);
pd[6] = OUTPUT(pd[6]_tri_out);


--pd[5] is pd[5]
--operation mode is output

pd[5]_tri_out = TRI(C1L24Q, C1L27Q);
pd[5] = OUTPUT(pd[5]_tri_out);


--pd[4] is pd[4]
--operation mode is output

pd[4]_tri_out = TRI(C1L23Q, C1L27Q);
pd[4] = OUTPUT(pd[4]_tri_out);


--pd[3] is pd[3]
--operation mode is output

pd[3]_tri_out = TRI(C1L22Q, C1L27Q);
pd[3] = OUTPUT(pd[3]_tri_out);


--pd[2] is pd[2]
--operation mode is output

pd[2]_tri_out = TRI(C1L21Q, C1L27Q);
pd[2] = OUTPUT(pd[2]_tri_out);


--pd[1] is pd[1]
--operation mode is output

pd[1]_tri_out = TRI(C1L20Q, C1L27Q);
pd[1] = OUTPUT(pd[1]_tri_out);


--pd[0] is pd[0]
--operation mode is output

pd[0]_tri_out = TRI(C1L19Q, C1L27Q);
pd[0] = OUTPUT(pd[0]_tri_out);