poc.vhd

简单的i/O接口的vhdl设计

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY POC IS
   PORT(CLK,RESET,CS,RDY,RW : IN STD_LOGIC;
         ADDR:IN STD_LOGIC_VECTOR(2 DOWNTO 0);
                DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
                TR,IRQ : OUT STD_LOGIC ;
                PD : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END POC;
ARCHITECTURE BEHAV OF POC IS
    SIGNAL SR : STD_LOGIC_VECTOR (7 DOWNTO 0 );
BEGIN
  PROCESS (CLK,RESET,CS,RDY,RW )
      VARIABLE BR : STD_LOGIC_VECTOR (7 DOWNTO 0 );
  BEGIN

   IF CLK'EVENT AND CLK='1' THEN
     IF RW ='1' AND ADDR="000" AND CS='1' THEN 
      BR := DATA ;
      SR <= "00000001";
     ELSE SR <= "10000001";
     END IF;
     IF RESET = '0' THEN 
        TR <= '0';
        SR <= "10000001";
     ELSIF RDY ='1' THEN 
            TR <= '1';
            PD <= BR ;
            SR(7) <= '1';
         ELSE TR <='0'; PD <= "ZZZZZZZZ";
     END IF;
      IRQ <= SR(0) AND SR(7);
    
   END IF ;
  END PROCESS ;
END ;