pocp.map.rpt

简单的i/O接口的vhdl设计

;     -- Combinational with no register       ; 15    ;
;     -- Register only                        ; 17    ;
;     -- Combinational with a register        ; 7     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 12    ;
;     -- 3 input functions                    ; 2     ;
;     -- 2 input functions                    ; 3     ;
;     -- 1 input functions                    ; 5     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 39    ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 4     ;
;                                             ;       ;
; Total registers                             ; 24    ;
; I/O pins                                    ; 24    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 23    ;
; Total fan-out                               ; 136   ;
; Average fan-out                             ; 2.16  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                          ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name        ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
; |pocp                      ; 39 (0)      ; 24           ; 0          ; 24   ; 0            ; 15 (0)       ; 17 (0)            ; 7 (0)            ; 0 (0)           ; 0 (0)      ; |pocp                      ;
;    |POC:inst1|             ; 29 (29)     ; 20           ; 0          ; 0    ; 0            ; 9 (9)        ; 17 (17)           ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |pocp|POC:inst1            ;
;    |printer:inst|          ; 10 (3)      ; 4            ; 0          ; 0    ; 0            ; 6 (3)        ; 0 (0)             ; 4 (0)            ; 0 (0)           ; 0 (0)      ; |pocp|printer:inst         ;
;       |74193:7|            ; 7 (7)       ; 4            ; 0          ; 0    ; 0            ; 3 (3)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |pocp|printer:inst|74193:7 ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; printer:inst|4~0                                       ;   ;
; printer:inst|74193:7|90~0                              ;   ;
; Number of logic cells representing combinational loops ; 2 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 24    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 9     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; printer:inst|74193:7|24                ; 2       ;
; printer:inst|74193:7|26                ; 3       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/pocp/pocp.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 15 17:45:02 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pocp -c pocp
Info: Found 2 design units, including 1 entities, in source file POC.vhd
    Info: Found design unit 1: POC-BEHAV
    Info: Found entity 1: POC
Info: Found 1 design units, including 1 entities, in source file printer.bdf
    Info: Found entity 1: printer
Info: Found 1 design units, including 1 entities, in source file pocp.bdf
    Info: Found entity 1: pocp
Info: Elaborating entity "pocp" for the top level hierarchy
Info: Elaborating entity "POC" for hierarchy "POC:inst1"
Info: Elaborating entity "printer" for hierarchy "printer:inst"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/others/maxplus2/74193.bdf
    Info: Found entity 1: 74193
Info: Elaborating entity "74193" for hierarchy "printer:inst|74193:7"
Info: Power-up level of register "POC:inst1|SR[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "POC:inst1|SR[0]" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "POC:inst1|process0~3" merged to single register "POC:inst1|process0~2"
    Info: Duplicate register "POC:inst1|process0~15" merged to single register "POC:inst1|process0~2"
    Info: Duplicate register "POC:inst1|process0~13" merged to single register "POC:inst1|process0~2"
    Info: Duplicate register "POC:inst1|process0~5" merged to single register "POC:inst1|process0~2"
    Info: Duplicate register "POC:inst1|process0~7" merged to single register "POC:inst1|process0~2"
    Info: Duplicate register "POC:inst1|process0~9" merged to single register "POC:inst1|process0~2"
    Info: Duplicate register "POC:inst1|process0~11" merged to single register "POC:inst1|process0~2"
Info: Registers with preset signals will power-up high
Info: Implemented 63 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 9 output pins
    Info: Implemented 39 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Mar 15 17:45:03 2009
    Info: Elapsed time: 00:00:02