pocp.tan.rpt

简单的i/O接口的vhdl设计

; N/A           ; None        ; -1.773 ns ; CS      ; POC:inst1|PD[0]~reg0 ; CLK      ;
; N/A           ; None        ; -1.793 ns ; addr[0] ; POC:inst1|PD[1]~reg0 ; CLK      ;
; N/A           ; None        ; -1.793 ns ; addr[0] ; POC:inst1|PD[0]~reg0 ; CLK      ;
; N/A           ; None        ; -1.876 ns ; data[5] ; POC:inst1|PD[5]~reg0 ; CLK      ;
; N/A           ; None        ; -1.991 ns ; addr[1] ; POC:inst1|PD[5]~reg0 ; CLK      ;
; N/A           ; None        ; -2.053 ns ; RW      ; POC:inst1|SR[7]      ; CLK      ;
; N/A           ; None        ; -2.053 ns ; RW      ; POC:inst1|BR[4]      ; CLK      ;
; N/A           ; None        ; -2.056 ns ; RW      ; POC:inst1|BR[7]      ; CLK      ;
; N/A           ; None        ; -2.120 ns ; addr[2] ; POC:inst1|SR[7]      ; CLK      ;
; N/A           ; None        ; -2.120 ns ; addr[2] ; POC:inst1|BR[4]      ; CLK      ;
; N/A           ; None        ; -2.123 ns ; addr[2] ; POC:inst1|BR[7]      ; CLK      ;
; N/A           ; None        ; -2.168 ns ; RW      ; POC:inst1|PD[6]~reg0 ; CLK      ;
; N/A           ; None        ; -2.176 ns ; CS      ; POC:inst1|SR[7]      ; CLK      ;
; N/A           ; None        ; -2.176 ns ; CS      ; POC:inst1|BR[4]      ; CLK      ;
; N/A           ; None        ; -2.179 ns ; CS      ; POC:inst1|BR[7]      ; CLK      ;
; N/A           ; None        ; -2.196 ns ; addr[0] ; POC:inst1|SR[7]      ; CLK      ;
; N/A           ; None        ; -2.196 ns ; addr[0] ; POC:inst1|BR[4]      ; CLK      ;
; N/A           ; None        ; -2.199 ns ; addr[0] ; POC:inst1|BR[7]      ; CLK      ;
; N/A           ; None        ; -2.235 ns ; addr[2] ; POC:inst1|PD[6]~reg0 ; CLK      ;
; N/A           ; None        ; -2.291 ns ; CS      ; POC:inst1|PD[6]~reg0 ; CLK      ;
; N/A           ; None        ; -2.311 ns ; addr[0] ; POC:inst1|PD[6]~reg0 ; CLK      ;
; N/A           ; None        ; -2.369 ns ; RW      ; POC:inst1|PD[4]~reg0 ; CLK      ;
; N/A           ; None        ; -2.436 ns ; addr[2] ; POC:inst1|PD[4]~reg0 ; CLK      ;
; N/A           ; None        ; -2.468 ns ; RW      ; POC:inst1|PD[7]~reg0 ; CLK      ;
; N/A           ; None        ; -2.492 ns ; CS      ; POC:inst1|PD[4]~reg0 ; CLK      ;
; N/A           ; None        ; -2.512 ns ; addr[0] ; POC:inst1|PD[4]~reg0 ; CLK      ;
; N/A           ; None        ; -2.534 ns ; CLK     ; POC:inst1|process0~2 ; CLK      ;
; N/A           ; None        ; -2.535 ns ; addr[2] ; POC:inst1|PD[7]~reg0 ; CLK      ;
; N/A           ; None        ; -2.591 ns ; CS      ; POC:inst1|PD[7]~reg0 ; CLK      ;
; N/A           ; None        ; -2.611 ns ; addr[0] ; POC:inst1|PD[7]~reg0 ; CLK      ;
; N/A           ; None        ; -2.619 ns ; RW      ; POC:inst1|PD[5]~reg0 ; CLK      ;
; N/A           ; None        ; -2.686 ns ; addr[2] ; POC:inst1|PD[5]~reg0 ; CLK      ;
; N/A           ; None        ; -2.742 ns ; CS      ; POC:inst1|PD[5]~reg0 ; CLK      ;
; N/A           ; None        ; -2.762 ns ; addr[0] ; POC:inst1|PD[5]~reg0 ; CLK      ;
; N/A           ; None        ; -2.958 ns ; CLK     ; POC:inst1|SR[7]      ; CLK      ;
+---------------+-------------+-----------+---------+----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Sun Mar 15 17:45:10 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pocp -c pocp
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 4 nodes
    Info: Node "printer:inst|2"
    Info: Node "printer:inst|4"
    Info: Node "printer:inst|74193:7|28~14"
    Info: Node "printer:inst|74193:7|28~15"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
    Info: Assuming node "RESET" is an undefined clock
Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "printer:inst|74193:7|6~11" as buffer
    Info: Detected gated clock "printer:inst|3" as buffer
    Info: Detected ripple clock "printer:inst|74193:7|25" as buffer
    Info: Detected ripple clock "printer:inst|74193:7|26" as buffer
    Info: Detected ripple clock "POC:inst1|TR" as buffer
    Info: Detected ripple clock "printer:inst|74193:7|24" as buffer
    Info: Detected gated clock "printer:inst|74193:7|28~14" as buffer
    Info: Detected gated clock "printer:inst|74193:7|28~15" as buffer
    Info: Detected gated clock "printer:inst|4" as buffer
    Info: Detected ripple clock "printer:inst|74193:7|23" as buffer
Info: Clock "CLK" has Internal fmax of 54.92 MHz between source register "printer:inst|74193:7|23" and destination register "POC:inst1|TR" (period= 18.208 ns)
    Info: + Longest register to register delay is 4.895 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N8; Fanout = 7; REG Node = 'printer:inst|74193:7|23'
        Info: 2: + IC(0.000 ns) + CELL(4.335 ns) = 4.335 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; COMB LOOP Node = 'printer:inst|74193:7|28~15'
            Info: Loc. = LC_X2_Y2_N6; Node "printer:inst|2"
            Info: Loc. = LC_X3_Y2_N6; Node "printer:inst|4"
            Info: Loc. = LC_X3_Y2_N1; Node "printer:inst|74193:7|28~15"
            Info: Loc. = LC_X3_Y2_N5; Node "printer:inst|74193:7|28~14"
        Info: 3: + IC(0.191 ns) + CELL(0.369 ns) = 4.895 ns; Loc. = LC_X3_Y2_N2; Fanout = 9; REG Node = 'POC:inst1|TR'
        Info: Total cell delay = 4.704 ns ( 96.10 % )
        Info: Total interconnect delay = 0.191 ns ( 3.90 % )
    Info: - Smallest clock skew is -12.870 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.093 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 27; CLK Node = 'CLK'
            Info: 2: + IC(0.792 ns) + CELL(0.574 ns) = 2.093 ns; Loc. = LC_X3_Y2_N2; Fanout = 9; REG Node = 'POC:inst1|TR'
            Info: Total cell delay = 1.301 ns ( 62.16 % )
            Info: Total interconnect delay = 0.792 ns ( 37.84 % )
        Info: - Longest clock path from clock "CLK" to source register is 14.963 ns
            Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_14; Fanout = 27; CLK Node = 'CLK'
            Info: 2: + IC(1.223 ns) + CELL(0.462 ns) = 2.412 ns; Loc. = LC_X4_Y2_N5; Fanout = 1; COMB Node = 'printer:inst|74193:7|6~11'
            Info: 3: + IC(0.420 ns) + CELL(0.809 ns) = 3.641 ns; Loc. = LC_X4_Y2_N4; Fanout = 6; REG Node = 'printer:inst|74193:7|25'
            Info: 4: + IC(0.000 ns) + CELL(0.946 ns) = 4.587 ns; Loc. = LC_X3_Y2_N5; Fanout = 2; COMB LOOP Node = 'printer:inst|74193:7|28~14'
                Info: Loc. = LC_X2_Y2_N6; Node "printer:inst|2"
                Info: Loc. = LC_X3_Y2_N6; Node "printer:inst|4"
                Info: Loc. = LC_X3_Y2_N1; Node "printer:inst|74193:7|28~15"
                Info: Loc. = LC_X3_Y2_N5; Node "printer:inst|74193:7|28~14"
            Info: 5: + IC(1.050 ns) + CELL(0.809 ns) = 6.446 ns; Loc. = LC_X3_Y3_N8; Fanout = 6; REG Node = 'printer:inst|74193:7|24'
            Info: 6: + IC(0.000 ns) + CELL(3.266 ns) = 9.712 ns; Loc. = LC_X3_Y2_N6; Fanout = 5; COMB LOOP Node = 'printer:inst|4'
                Info: Loc. = LC_X2_Y2_N6; Node "printer:inst|2"
                Info: Loc. = LC_X3_Y2_N6; Node "printer:inst|4"
                Info: Loc. = LC_X3_Y2_N1; Node "printer:inst|74193:7|28~15"
                Info: Loc. = LC_X3_Y2_N5; Node "printer:inst|74193:7|28~14"
            Info: 7: + IC(0.748 ns) + CELL(0.319 ns) = 10.779 ns; Loc. = LC_X4_Y2_N6; Fanout = 1; COMB Node = 'printer:inst|3'
            Info: 8: + IC(0.420 ns) + CELL(0.809 ns) = 12.008 ns; Loc. = LC_X4_Y2_N9; Fanout = 7; REG Node = 'printer:inst|74193:7|26'
            Info: 9: + IC(0.000 ns) + CELL(1.962 ns) = 13.970 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; COMB LOOP Node = 'printer:inst|74193:7|28~15'
                Info: Loc. = LC_X2_Y2_N6; Node "printer:inst|2"
                Info: Loc. = LC_X3_Y2_N6; Node "printer:inst|4"
                Info: Loc. = LC_X3_Y2_N1; Node "printer:inst|74193:7|28~15"
                Info: Loc. = LC_X3_Y2_N5; Node "printer:inst|74193:7|28~14"
            Info: 10: + IC(0.419 ns) + CELL(0.574 ns) = 14.963 ns; Loc. = LC_X3_Y2_N8; Fanout = 7; REG Node = 'printer:inst|74193:7|23'
            Info: Total cell delay = 10.683 ns ( 71.40 % )
            Info: Total interconnect delay = 4.280 ns ( 28.60 % )
    Info: + Micro clock to output delay of source is 0.235 ns
    Info: + Micro setup delay of destination is 0.208 ns
Info: Clock "RESET" has Internal fmax of 163.72 MHz between source register "printer:inst|74193:7|23" and destination register "printer:inst|74193:7|23" (period= 6.108 ns)
    Info: + Longest register to register delay is 0.940 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N8; Fanout = 7; REG Node = 'printer:inst|74193:7|23'
        Info: 2: + IC(0.571 ns) + CELL(0.369 ns) = 0.940 ns; Loc. = LC_X3_Y2_N8; Fanout = 7; REG Node = 'printer:inst|74193:7|23'
        Info: Total cell delay = 0.369 ns ( 39.26 % )
        Info: Total interconnect delay = 0.571 ns ( 60.74 % )
    Info: - Smallest clock skew is -4.725 ns
        Info: + Shortest clock path from clock "RESET" to destination register is 6.929 ns
            Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_8; Fanout = 15; CLK Node = 'RESET'
            Info: 2: + IC(0.000 ns) + CELL(5.228 ns) = 5.936 ns; Loc. = LC_X3_Y2_N1; Fanout = 3; COMB LOOP Node = 'printer:inst|74193:7|28~15'
                Info: Loc. = LC_X2_Y2_N6; Node "printer:inst|2"
                Info: Loc. = LC_X3_Y2_N6; Node "printer:inst|4"
                Info: Loc. = LC_X3_Y2_N1; Node "printer:inst|74193:7|28~15"
                Info: Loc. = LC_X3_Y2_N5; Node "printer:inst|74193:7|28~14"
            Info: 3: + IC(0.419 ns) + CELL(0.574 ns) = 6.929 ns; Loc. = LC_X3_Y2_N8; Fanout = 7; REG Node = 'printer:inst|74193:7|23'
            Info: Total cell delay = 6.510 ns ( 93.95 % )
            Info: Total interconnect delay = 0.419 ns ( 6.05 % )
        Info: - Longest clock path from clock "RESET" to source register is 11.654 ns
            Info: 1: + IC(0.000 ns) + CELL(0.708 ns) = 0.708 ns; Loc. = PIN_8; Fanout = 15; CLK Node = 'RESET'
            Info: 2: + IC(0.000 ns) + CELL(3.259 ns) = 3.967 ns; Loc. = LC_X3_Y2_N6; Fanout = 5; COMB LOOP Node = 'printer:inst|4'
                Info: Loc. = LC_X2_Y2_N6; Node "printer:inst|2"
                Info: Loc. = LC_X3_Y2_N6; Node "printer:inst|4"
                Info: Loc. = LC_X3_Y2_N1; Node "printer:inst|74193:7|28~15"