📄 pocp.tan.rpt
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Timing Analyzer report for pocp
Sun Mar 15 17:45:11 2009
Version 5.1 Build 176 10/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CLK'
6. Clock Setup: 'RESET'
7. Clock Hold: 'CLK'
8. Clock Hold: 'RESET'
9. tsu
10. tco
11. th
12. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------+-------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------+-------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 4.611 ns ; RESET ; POC:inst1|TR ; -- ; CLK ; 0 ;
; Worst-case tco ; N/A ; None ; 4.677 ns ; POC:inst1|PD[6]~reg0 ; pd[6] ; CLK ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -0.686 ns ; data[5] ; POC:inst1|BR[5] ; -- ; CLK ; 0 ;
; Clock Setup: 'CLK' ; N/A ; None ; 54.92 MHz ( period = 18.208 ns ) ; printer:inst|74193:7|23 ; POC:inst1|TR ; CLK ; CLK ; 0 ;
; Clock Setup: 'RESET' ; N/A ; None ; 163.72 MHz ( period = 6.108 ns ) ; printer:inst|74193:7|23 ; printer:inst|74193:7|23 ; RESET ; RESET ; 0 ;
; Clock Hold: 'CLK' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; printer:inst|74193:7|23 ; printer:inst|74193:7|23 ; CLK ; CLK ; 3 ;
; Clock Hold: 'RESET' ; Not operational: Clock Skew > Data Delay ; None ; N/A ; printer:inst|74193:7|23 ; printer:inst|74193:7|23 ; RESET ; RESET ; 2 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 5 ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------+-------------------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPM240T100C3 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; RESET ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK' ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-------------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 54.92 MHz ( period = 18.208 ns ) ; printer:inst|74193:7|23 ; POC:inst1|TR ; CLK ; CLK ; None ; None ; 4.895 ns ;
; N/A ; 64.09 MHz ( period = 15.602 ns ) ; printer:inst|74193:7|23 ; POC:inst1|SR[7] ; CLK ; CLK ; None ; None ; 2.289 ns ;
; N/A ; 65.88 MHz ( period = 15.178 ns ) ; printer:inst|74193:7|23 ; POC:inst1|process0~2 ; CLK ; CLK ; None ; None ; 1.865 ns ;
; N/A ; 66.86 MHz ( period = 14.956 ns ) ; printer:inst|74193:7|24 ; POC:inst1|TR ; CLK ; CLK ; None ; None ; 4.249 ns ;
; N/A ; 71.96 MHz ( period = 13.896 ns ) ; printer:inst|74193:7|24 ; POC:inst1|SR[7] ; CLK ; CLK ; None ; None ; 3.189 ns ;
; N/A ; 74.23 MHz ( period = 13.472 ns ) ; printer:inst|74193:7|24 ; POC:inst1|process0~2 ; CLK ; CLK ; None ; None ; 2.765 ns ;
; N/A ; 79.87 MHz ( period = 12.520 ns ) ; printer:inst|74193:7|26 ; POC:inst1|TR ; CLK ; CLK ; None ; None ; 4.833 ns ;
; N/A ; 83.51 MHz ( period = 11.975 ns ) ; printer:inst|74193:7|23 ; printer:inst|74193:7|23 ; CLK ; CLK ; None ; None ; 0.940 ns ;
; N/A ; 87.26 MHz ( period = 11.460 ns ) ; printer:inst|74193:7|26 ; POC:inst1|SR[7] ; CLK ; CLK ; None ; None ; 3.773 ns ;
; N/A ; 90.61 MHz ( period = 11.036 ns ) ; printer:inst|74193:7|26 ; POC:inst1|process0~2 ; CLK ; CLK ; None ; None ; 3.349 ns ;
; N/A ; 104.98 MHz ( period = 9.526 ns ) ; printer:inst|74193:7|24 ; printer:inst|74193:7|24 ; CLK ; CLK ; None ; None ; 0.927 ns ;
; N/A ; 130.67 MHz ( period = 7.653 ns ) ; printer:inst|74193:7|26 ; printer:inst|74193:7|26 ; CLK ; CLK ; None ; None ; 0.941 ns ;
; N/A ; 156.89 MHz ( period = 6.374 ns ) ; printer:inst|74193:7|25 ; POC:inst1|TR ; CLK ; CLK ; None ; None ; 4.618 ns ;
; N/A ; 188.18 MHz ( period = 5.314 ns ) ; printer:inst|74193:7|25 ; POC:inst1|SR[7] ; CLK ; CLK ; None ; None ; 3.558 ns ;
; N/A ; 203.42 MHz ( period = 4.916 ns ) ; POC:inst1|TR ; POC:inst1|SR[7] ; CLK ; CLK ; None ; None ; 4.473 ns ;
; N/A ; 204.50 MHz ( period = 4.890 ns ) ; printer:inst|74193:7|25 ; POC:inst1|process0~2 ; CLK ; CLK ; None ; None ; 3.134 ns ;
; N/A ; 222.62 MHz ( period = 4.492 ns ) ; POC:inst1|TR ; POC:inst1|process0~2 ; CLK ; CLK ; None ; None ; 4.049 ns ;
; N/A ; 272.85 MHz ( period = 3.665 ns ) ; POC:inst1|TR ; POC:inst1|TR ; CLK ; CLK ; None ; None ; 3.222 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[5] ; POC:inst1|PD[5]~reg0 ; CLK ; CLK ; None ; None ; 1.730 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; printer:inst|74193:7|25 ; printer:inst|74193:7|25 ; CLK ; CLK ; None ; None ; 1.601 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|SR[7] ; POC:inst1|IRQ ; CLK ; CLK ; None ; None ; 1.346 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[6] ; POC:inst1|PD[6]~reg0 ; CLK ; CLK ; None ; None ; 1.279 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[7] ; POC:inst1|PD[7]~reg0 ; CLK ; CLK ; None ; None ; 1.028 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[0] ; POC:inst1|PD[0]~reg0 ; CLK ; CLK ; None ; None ; 1.022 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[1] ; POC:inst1|PD[1]~reg0 ; CLK ; CLK ; None ; None ; 1.021 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[2] ; POC:inst1|PD[2]~reg0 ; CLK ; CLK ; None ; None ; 0.932 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[3] ; POC:inst1|PD[3]~reg0 ; CLK ; CLK ; None ; None ; 0.932 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[4] ; POC:inst1|PD[4]~reg0 ; CLK ; CLK ; None ; None ; 0.932 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[0] ; POC:inst1|BR[0] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[1] ; POC:inst1|BR[1] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[2] ; POC:inst1|BR[2] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[3] ; POC:inst1|BR[3] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[4] ; POC:inst1|BR[4] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[5] ; POC:inst1|BR[5] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[6] ; POC:inst1|BR[6] ; CLK ; CLK ; None ; None ; 0.577 ns ;
; N/A ; Restricted to 304.04 MHz ( period = 3.289 ns ) ; POC:inst1|BR[7] ; POC:inst1|BR[7] ; CLK ; CLK ; None ; None ; 0.577 ns ;
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