szsz.map.rpt

该文件是用VHDL变成实现的数字钟程序

; aglobal80.inc                    ; yes             ; Megafunction    ; e:/quartus ii 8.0/quartus/libraries/megafunctions/aglobal80.inc           ;
; alt_counter_f10ke.tdf            ; yes             ; Megafunction    ; e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf   ;
; flex10ke_lcell.inc               ; yes             ; Megafunction    ; e:/quartus ii 8.0/quartus/libraries/megafunctions/flex10ke_lcell.inc      ;
+----------------------------------+-----------------+-----------------+---------------------------------------------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Total logic elements              ; 15      ;
; Total combinational functions     ; 15      ;
;     -- Total 4-input functions    ; 4       ;
;     -- Total 3-input functions    ; 3       ;
;     -- Total 2-input functions    ; 3       ;
;     -- Total 1-input functions    ; 5       ;
;     -- Total 0-input functions    ; 0       ;
; Total registers                   ; 8       ;
; Total logic cells in carry chains ; 4       ;
; I/O pins                          ; 10      ;
; Maximum fan-out node              ; reset   ;
; Maximum fan-out                   ; 8       ;
; Total fan-out                     ; 67      ;
; Average fan-out                   ; 2.68    ;
+-----------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                           ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------+--------------+
; Compilation Hierarchy Node             ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name                                            ; Library Name ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------+--------------+
; |hour                                  ; 15 (11)     ; 8            ; 0           ; 10   ; 7 (7)        ; 0 (0)             ; 8 (4)            ; 4 (0)           ; 0 (0)      ; |hour                                                          ; work         ;
;    |lpm_counter:hour1_t_rtl_0|         ; 4 (0)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (0)            ; 4 (0)           ; 0 (0)      ; |hour|lpm_counter:hour1_t_rtl_0                                ; work         ;
;       |alt_counter_f10ke:wysi_counter| ; 4 (4)       ; 4            ; 0           ; 0    ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 4 (4)           ; 0 (0)      ; |hour|lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter ; work         ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 4     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 4     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Source assignments for lpm_counter:hour1_t_rtl_0 ;
+---------------------------+-------+------+-------+
; Assignment                ; Value ; From ; To    ;
+---------------------------+-------+------+-------+
; SUPPRESS_DA_RULE_INTERNAL ; a101  ; -    ; -     ;
; SUPPRESS_DA_RULE_INTERNAL ; s102  ; -    ; -     ;
; SUPPRESS_DA_RULE_INTERNAL ; s103  ; -    ; -     ;
+---------------------------+-------+------+-------+


+----------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: lpm_counter:hour1_t_rtl_0 ;
+------------------------+-------------------+-------------------------------+
; Parameter Name         ; Value             ; Type                          ;
+------------------------+-------------------+-------------------------------+
; AUTO_CARRY_CHAINS      ; ON                ; AUTO_CARRY                    ;
; IGNORE_CARRY_BUFFERS   ; OFF               ; IGNORE_CARRY                  ;
; AUTO_CASCADE_CHAINS    ; ON                ; AUTO_CASCADE                  ;
; IGNORE_CASCADE_BUFFERS ; OFF               ; IGNORE_CASCADE                ;
; LPM_WIDTH              ; 4                 ; Untyped                       ;
; LPM_DIRECTION          ; UP                ; Untyped                       ;
; LPM_MODULUS            ; 0                 ; Untyped                       ;
; LPM_AVALUE             ; UNUSED            ; Untyped                       ;
; LPM_SVALUE             ; UNUSED            ; Untyped                       ;
; LPM_PORT_UPDOWN        ; PORT_CONNECTIVITY ; Untyped                       ;
; DEVICE_FAMILY          ; ACEX1K            ; Untyped                       ;
; CARRY_CHAIN            ; MANUAL            ; Untyped                       ;
; CARRY_CHAIN_LENGTH     ; 48                ; CARRY_CHAIN_LENGTH            ;
; NOT_GATE_PUSH_BACK     ; ON                ; NOT_GATE_PUSH_BACK            ;
; CARRY_CNT_EN           ; SMART             ; Untyped                       ;
; LABWIDE_SCLR           ; ON                ; Untyped                       ;
; USE_NEW_VERSION        ; TRUE              ; Untyped                       ;
; CBXI_PARAMETER         ; NOTHING           ; Untyped                       ;
+------------------------+-------------------+-------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Web Edition
    Info: Processing started: Thu Nov 13 16:12:23 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off szsz -c szsz
Info: Found 2 design units, including 1 entities, in source file second.vhd
    Info: Found design unit 1: second-rt1
    Info: Found entity 1: second
Info: Found 2 design units, including 1 entities, in source file minute.vhd
    Info: Found design unit 1: minute-rt2
    Info: Found entity 1: minute
Info: Found 2 design units, including 1 entities, in source file hour.vhd
    Info: Found design unit 1: hour-rt3
    Info: Found entity 1: hour
Info: Elaborating entity "hour" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at hour.vhd(33): signal "hour1_t" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at hour.vhd(34): signal "hour2_t" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "hour1_t[0]~12"
Info: Elaborated megafunction instantiation "lpm_counter:hour1_t_rtl_0"
Info: Instantiated megafunction "lpm_counter:hour1_t_rtl_0" with the following parameter:
    Info: Parameter "LPM_WIDTH" = "4"
    Info: Parameter "LPM_DIRECTION" = "UP"
    Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Info: Elaborated megafunction instantiation "lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "lpm_counter:hour1_t_rtl_0"
Info: Implemented 25 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 8 output pins
    Info: Implemented 15 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 177 megabytes
    Info: Processing ended: Thu Nov 13 16:12:35 2008
    Info: Elapsed time: 00:00:12
    Info: Total CPU time (on all processors): 00:00:04