szsz.tan.qmsg

该文件是用VHDL变成实现的数字钟程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 5 -1 0 } } { "e:/quartus ii 8.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus ii 8.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] register lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 75.19 MHz 13.3 ns Internal " "Info: Clock \"clk\" has Internal fmax of 75.19 MHz between source register \"lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]\" and destination register \"lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]\" (period= 13.3 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.500 ns + Longest register register " "Info: + Longest register to register delay is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 1 REG LC4_A45 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_A45; Fanout = 4; REG Node = 'lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(2.200 ns) 3.200 ns process0~54 2 COMB LC6_A46 1 " "Info: 2: + IC(1.000 ns) + CELL(2.200 ns) = 3.200 ns; Loc. = LC6_A46; Fanout = 1; COMB Node = 'process0~54'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] process0~54 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 5.300 ns process0~0 3 COMB LC1_A46 3 " "Info: 3: + IC(0.200 ns) + CELL(1.900 ns) = 5.300 ns; Loc. = LC1_A46; Fanout = 3; COMB Node = 'process0~0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { process0~54 process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 8.100 ns hour1_t~39 4 COMB LC8_A45 3 " "Info: 4: + IC(1.100 ns) + CELL(1.700 ns) = 8.100 ns; Loc. = LC8_A45; Fanout = 3; COMB Node = 'hour1_t~39'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { process0~0 hour1_t~39 } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 10.000 ns hour1_t~39_wirecell 5 COMB LC6_A45 4 " "Info: 5: + IC(0.200 ns) + CELL(1.700 ns) = 10.000 ns; Loc. = LC6_A45; Fanout = 4; COMB Node = 'hour1_t~39_wirecell'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { hour1_t~39 hour1_t~39_wirecell } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.300 ns) 11.500 ns lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 6 REG LC1_A45 6 " "Info: 6: + IC(0.200 ns) + CELL(1.300 ns) = 11.500 ns; Loc. = LC1_A45; Fanout = 6; REG Node = 'lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { hour1_t~39_wirecell lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.800 ns ( 76.52 % ) " "Info: Total cell delay = 8.800 ns ( 76.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 23.48 % ) " "Info: Total interconnect delay = 2.700 ns ( 23.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] process0~54 process0~0 hour1_t~39 hour1_t~39_wirecell lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] {} process0~54 {} process0~0 {} hour1_t~39 {} hour1_t~39_wirecell {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] {} } { 0.000ns 1.000ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 2.200ns 1.900ns 1.700ns 1.700ns 1.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\] 2 REG LC1_A45 6 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_A45; Fanout = 6; REG Node = 'lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[0\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\] 2 REG LC4_A45 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC4_A45; Fanout = 4; REG Node = 'lpm_counter:hour1_t_rtl_0\|alt_counter_f10ke:wysi_counter\|q\[3\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "alt_counter_f10ke.tdf" "" { Text "e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "e:/quartus ii 8.0/quartus/libraries/megafunctions/alt_counter_f10ke.tdf" 289 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] process0~54 process0~0 hour1_t~39 hour1_t~39_wirecell lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] {} process0~54 {} process0~0 {} hour1_t~39 {} hour1_t~39_wirecell {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] {} } { 0.000ns 1.000ns 0.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 2.200ns 1.900ns 1.700ns 1.700ns 1.300ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} lpm_counter:hour1_t_rtl_0|alt_counter_f10ke:wysi_counter|q[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk hour2\[3\] hour2_t\[3\] 14.800 ns register " "Info: tco from clock \"clk\" to destination pin \"hour2\[3\]\" through register \"hour2_t\[3\]\" is 14.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 8 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 8; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns hour2_t\[3\] 2 REG LC3_A46 4 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_A46; Fanout = 4; REG Node = 'hour2_t\[3\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk hour2_t[3] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk hour2_t[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} hour2_t[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 13 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.800 ns + Longest register pin " "Info: + Longest register to pin delay is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns hour2_t\[3\] 1 REG LC3_A46 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_A46; Fanout = 4; REG Node = 'hour2_t\[3\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { hour2_t[3] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.200 ns) + CELL(8.600 ns) 11.800 ns hour2\[3\] 2 PIN PIN_39 0 " "Info: 2: + IC(3.200 ns) + CELL(8.600 ns) = 11.800 ns; Loc. = PIN_39; Fanout = 0; PIN Node = 'hour2\[3\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { hour2_t[3] hour2[3] } "NODE_NAME" } } { "hour.vhd" "" { Text "E:/EDADesign/zyz/hour.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 72.88 % ) " "Info: Total cell delay = 8.600 ns ( 72.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.200 ns ( 27.12 % ) " "Info: Total interconnect delay = 3.200 ns ( 27.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { hour2_t[3] hour2[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { hour2_t[3] {} hour2[3] {} } { 0.000ns 3.200ns } { 0.000ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk hour2_t[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} hour2_t[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { hour2_t[3] hour2[3] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { hour2_t[3] {} hour2[3] {} } { 0.000ns 3.200ns } { 0.000ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "128 " "Info: Peak virtual memory: 128 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 13 16:13:16 2008 " "Info: Processing ended: Thu Nov 13 16:13:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}