prev_cmp_szsz.tan.qmsg

该文件是用VHDL变成实现的数字钟程序

{ "Info" "ITDB_FULL_TCO_RESULT" "clk min1\[1\] min1_t\[1\] 14.500 ns register " "Info: tco from clock \"clk\" to destination pin \"min1\[1\]\" through register \"min1_t\[1\]\" is 14.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns min1_t\[1\] 2 REG LC7_A51 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC7_A51; Fanout = 5; REG Node = 'min1_t\[1\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk min1_t[1] } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk min1_t[1] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} min1_t[1] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.500 ns + Longest register pin " "Info: + Longest register to pin delay is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min1_t\[1\] 1 REG LC7_A51 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A51; Fanout = 5; REG Node = 'min1_t\[1\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { min1_t[1] } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(8.600 ns) 11.500 ns min1\[1\] 2 PIN PIN_27 0 " "Info: 2: + IC(2.900 ns) + CELL(8.600 ns) = 11.500 ns; Loc. = PIN_27; Fanout = 0; PIN Node = 'min1\[1\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { min1_t[1] min1[1] } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 74.78 % ) " "Info: Total cell delay = 8.600 ns ( 74.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 25.22 % ) " "Info: Total interconnect delay = 2.900 ns ( 25.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { min1_t[1] min1[1] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { min1_t[1] {} min1[1] {} } { 0.000ns 2.900ns } { 0.000ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk min1_t[1] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} min1_t[1] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { min1_t[1] min1[1] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { min1_t[1] {} min1[1] {} } { 0.000ns 2.900ns } { 0.000ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "carry~reg0 reset clk -1.300 ns register " "Info: th for register \"carry~reg0\" (data pin = \"reset\", clock pin = \"clk\") is -1.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns carry~reg0 2 REG LC8_A52 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_A52; Fanout = 1; REG Node = 'carry~reg0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk carry~reg0 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.900 ns + " "Info: + Micro hold delay of destination is 0.900 ns" {  } { { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns reset 1 PIN PIN_184 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 9; PIN Node = 'reset'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.700 ns) 3.600 ns carry~5 2 COMB LC5_A52 1 " "Info: 2: + IC(1.400 ns) + CELL(1.700 ns) = 3.600 ns; Loc. = LC5_A52; Fanout = 1; COMB Node = 'carry~5'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { reset carry~5 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 4.100 ns carry~reg0 3 REG LC8_A52 1 " "Info: 3: + IC(0.200 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC8_A52; Fanout = 1; REG Node = 'carry~reg0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.500 ns" { carry~5 carry~reg0 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 60.98 % ) " "Info: Total cell delay = 2.500 ns ( 60.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 39.02 % ) " "Info: Total interconnect delay = 1.600 ns ( 39.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { reset carry~5 carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "4.100 ns" { reset {} reset~out {} carry~5 {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.700ns 0.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { reset carry~5 carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "4.100 ns" { reset {} reset~out {} carry~5 {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.700ns 0.300ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "128 " "Info: Peak virtual memory: 128 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 13 16:02:08 2008 " "Info: Processing ended: Thu Nov 13 16:02:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}