prev_cmp_szsz.tan.qmsg

该文件是用VHDL变成实现的数字钟程序

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } } { "e:/quartus ii 8.0/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus ii 8.0/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register min1_t\[0\] register carry~reg0 161.29 MHz 6.2 ns Internal " "Info: Clock \"clk\" has Internal fmax of 161.29 MHz between source register \"min1_t\[0\]\" and destination register \"carry~reg0\" (period= 6.2 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns + Longest register register " "Info: + Longest register to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min1_t\[0\] 1 REG LC2_A51 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_A51; Fanout = 6; REG Node = 'min1_t\[0\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { min1_t[0] } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 2.400 ns Equal0~31 2 COMB LC4_A51 7 " "Info: 2: + IC(0.200 ns) + CELL(2.200 ns) = 2.400 ns; Loc. = LC4_A51; Fanout = 7; COMB Node = 'Equal0~31'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { min1_t[0] Equal0~31 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/quartus ii 8.0/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.000 ns) 4.400 ns carry~reg0 3 REG LC8_A52 1 " "Info: 3: + IC(1.000 ns) + CELL(1.000 ns) = 4.400 ns; Loc. = LC8_A52; Fanout = 1; REG Node = 'carry~reg0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { Equal0~31 carry~reg0 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.200 ns ( 72.73 % ) " "Info: Total cell delay = 3.200 ns ( 72.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.200 ns ( 27.27 % ) " "Info: Total interconnect delay = 1.200 ns ( 27.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { min1_t[0] Equal0~31 carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "4.400 ns" { min1_t[0] {} Equal0~31 {} carry~reg0 {} } { 0.000ns 0.200ns 1.000ns } { 0.000ns 2.200ns 1.000ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns carry~reg0 2 REG LC8_A52 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_A52; Fanout = 1; REG Node = 'carry~reg0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk carry~reg0 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns min1_t\[0\] 2 REG LC2_A51 6 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_A51; Fanout = 6; REG Node = 'min1_t\[0\]'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk min1_t[0] } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk min1_t[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} min1_t[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk min1_t[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} min1_t[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.400 ns" { min1_t[0] Equal0~31 carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "4.400 ns" { min1_t[0] {} Equal0~31 {} carry~reg0 {} } { 0.000ns 0.200ns 1.000ns } { 0.000ns 2.200ns 1.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk min1_t[0] } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} min1_t[0] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "carry~reg0 reset clk 2.900 ns register " "Info: tsu for register \"carry~reg0\" (data pin = \"reset\", clock pin = \"clk\") is 2.900 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.100 ns + Longest pin register " "Info: + Longest pin to register delay is 4.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns reset 1 PIN PIN_184 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_184; Fanout = 9; PIN Node = 'reset'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.700 ns) 3.600 ns carry~5 2 COMB LC5_A52 1 " "Info: 2: + IC(1.400 ns) + CELL(1.700 ns) = 3.600 ns; Loc. = LC5_A52; Fanout = 1; COMB Node = 'carry~5'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { reset carry~5 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 4.100 ns carry~reg0 3 REG LC8_A52 1 " "Info: 3: + IC(0.200 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC8_A52; Fanout = 1; REG Node = 'carry~reg0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "0.500 ns" { carry~5 carry~reg0 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 60.98 % ) " "Info: Total cell delay = 2.500 ns ( 60.98 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 39.02 % ) " "Info: Total interconnect delay = 1.600 ns ( 39.02 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { reset carry~5 carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "4.100 ns" { reset {} reset~out {} carry~5 {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.700ns 0.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clk 1 CLK PIN_79 9 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_79; Fanout = 9; CLK Node = 'clk'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns carry~reg0 2 REG LC8_A52 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_A52; Fanout = 1; REG Node = 'carry~reg0'" {  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { clk carry~reg0 } "NODE_NAME" } } { "minute.vhd" "" { Text "E:/EDADesign/zyz/minute.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { reset carry~5 carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "4.100 ns" { reset {} reset~out {} carry~5 {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns 0.200ns } { 0.000ns 0.500ns 1.700ns 0.300ns } "" } } { "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus ii 8.0/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { clk carry~reg0 } "NODE_NAME" } } { "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus ii 8.0/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { clk {} clk~out {} carry~reg0 {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}