_primary.vhd

基于quartus II软件 用verilog 语言描述的精简指令CPU

library verilog;
use verilog.vl_types.all;
entity alu_risc is
    generic(
        WORD_SIZE       : integer := 8;
        OP_SIZE         : integer := 4;
        NOP             : integer := 0;
        ADD             : integer := 1;
        SUB             : integer := 2;
        \AND\           : integer := 3;
        \NOT\           : integer := 4;
        RD              : integer := 5;
        WR              : integer := 6;
        BR              : integer := 7;
        BRZ             : integer := 8
    );
    port(
        alu_zero_flag   : out    vl_logic;
        alu_out         : out    vl_logic_vector;
        data_1          : in     vl_logic_vector;
        data_2          : in     vl_logic_vector;
        sel             : in     vl_logic_vector
    );
end alu_risc;