_primary.vhd

基于quartus II软件 用verilog 语言描述的精简指令CPU

library verilog;
use verilog.vl_types.all;
entity RISC_SPM is
    generic(
        WORD_SIZE       : integer := 8;
        SEL1_SIZE       : integer := 3;
        SEL2_SIZE       : integer := 2
    );
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end RISC_SPM;