_primary.vhd

来自「基于quartus II软件 用verilog 语言描述的精简指令CPU」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity multiplexer_3ch is
    generic(
        WORD_SIZE       : integer := 8
    );
    port(
        mux_out         : out    vl_logic_vector;
        data_a          : in     vl_logic_vector;
        data_b          : in     vl_logic_vector;
        data_c          : in     vl_logic_vector;
        sel             : in     vl_logic_vector(1 downto 0)
    );
end multiplexer_3ch;