_primary.vhd

来自「基于quartus II软件 用verilog 语言描述的精简指令CPU」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity address_register is
    generic(
        WORD_SIZE       : integer := 8
    );
    port(
        data_out        : out    vl_logic_vector;
        data_in         : in     vl_logic_vector;
        load            : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end address_register;