_primary.vhd

来自「基于quartus II软件 用verilog 语言描述的精简指令CPU」· VHDL 代码 · 共 58 行

library verilog;
use verilog.vl_types.all;
entity control_unit is
    generic(
        WORD_SIZE       : integer := 8;
        OP_SIZE         : integer := 4;
        STATE_SIZE      : integer := 4;
        SRC_SIZE        : integer := 2;
        DEST_SIZE       : integer := 2;
        SEL1_SIZE       : integer := 3;
        SEL2_SIZE       : integer := 2;
        S_idle          : integer := 0;
        S_fet1          : integer := 1;
        S_fet2          : integer := 2;
        S_dec           : integer := 3;
        S_ex1           : integer := 4;
        S_rd1           : integer := 5;
        S_rd2           : integer := 6;
        S_wr1           : integer := 7;
        S_wr2           : integer := 8;
        S_br1           : integer := 9;
        S_br2           : integer := 10;
        S_halt          : integer := 11;
        NOP             : integer := 0;
        ADD             : integer := 1;
        SUB             : integer := 2;
        \AND\           : integer := 3;
        \NOT\           : integer := 4;
        RD              : integer := 5;
        WR              : integer := 6;
        BR              : integer := 7;
        BRZ             : integer := 8;
        R0              : integer := 0;
        R1              : integer := 1;
        R2              : integer := 2;
        R3              : integer := 3
    );
    port(
        load_r0         : out    vl_logic;
        load_r1         : out    vl_logic;
        load_r2         : out    vl_logic;
        load_r3         : out    vl_logic;
        load_pc         : out    vl_logic;
        inc_pc          : out    vl_logic;
        sel_bus_1_mux   : out    vl_logic_vector;
        sel_bus_2_mux   : out    vl_logic_vector;
        load_ir         : out    vl_logic;
        load_add_r      : out    vl_logic;
        load_reg_y      : out    vl_logic;
        load_reg_z      : out    vl_logic;
        write           : out    vl_logic;
        instruction     : in     vl_logic_vector;
        zero            : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end control_unit;