_primary.vhd

来自「基于quartus II软件 用verilog 语言描述的精简指令CPU」· VHDL 代码 · 共 32 行

library verilog;
use verilog.vl_types.all;
entity processing_unit is
    generic(
        WORD_SIZE       : integer := 8;
        OP_SIZE         : integer := 4;
        SEL1_SIZE       : integer := 3;
        SEL2_SIZE       : integer := 2
    );
    port(
        instruction     : out    vl_logic_vector;
        zflag           : out    vl_logic;
        address         : out    vl_logic_vector;
        bus_1           : out    vl_logic_vector;
        mem_word        : in     vl_logic_vector;
        load_r0         : in     vl_logic;
        load_r1         : in     vl_logic;
        load_r2         : in     vl_logic;
        load_r3         : in     vl_logic;
        load_pc         : in     vl_logic;
        inc_pc          : in     vl_logic;
        sel_bus_1_mux   : in     vl_logic_vector;
        load_ir         : in     vl_logic;
        load_add_r      : in     vl_logic;
        load_reg_y      : in     vl_logic;
        load_reg_z      : in     vl_logic;
        sel_bus_2_mux   : in     vl_logic_vector;
        clk             : in     vl_logic;
        rst             : in     vl_logic
    );
end processing_unit;