watch.map.summary

来自「基于quartus II软件 用verilog 语言描述的一个秒表」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Thu Nov 27 21:25:14 2008
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : watch
Top-level Entity Name : watch
Family : Cyclone II
Total logic elements : 58
    Total combinational functions : 58
    Dedicated logic registers : 6
Total registers : 6
Total pins : 16
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0