prev_cmp_watch.map.qmsg

基于quartus II软件 用verilog 语言描述的一个秒表

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 21:05:20 2008 " "Info: Processing started: Thu Nov 27 21:05:20 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off watch -c watch " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off watch -c watch" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "watch.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file watch.v" { { "Info" "ISGN_ENTITY_NAME" "1 watch " "Info: Found entity 1: watch" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "watch " "Info: Elaborating entity \"watch\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "display1 watch.v(13) " "Warning (10240): Verilog HDL Always Construct warning at watch.v(13): inferring latch(es) for variable \"display1\", which holds its previous value in one or more paths through the always construct" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 13 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "watch.v(28) " "Warning (10270): Verilog HDL Case Statement warning at watch.v(28): incomplete case statement has no default case item" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 28 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "display2 watch.v(27) " "Warning (10240): Verilog HDL Always Construct warning at watch.v(27): inferring latch(es) for variable \"display2\", which holds its previous value in one or more paths through the always construct" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[0\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[0\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[1\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[1\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[2\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[2\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[3\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[3\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[4\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[4\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[5\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[5\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display2\[6\] watch.v(27) " "Info (10041): Inferred latch for \"display2\[6\]\" at watch.v(27)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[0\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[0\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[1\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[1\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[2\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[2\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[3\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[3\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[4\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[4\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[5\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[5\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "display1\[6\] watch.v(17) " "Info (10041): Inferred latch for \"display1\[6\]\" at watch.v(17)" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DUP_LATCH_INFO_HDR" "" "Info: Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IOPT_MLS_DUP_LATCH_INFO" "display2\[6\]\$latch display2\[0\]\$latch " "Info: Duplicate LATCH primitive \"display2\[6\]\$latch\" merged with LATCH primitive \"display2\[0\]\$latch\"" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "display2\[0\]\$latch " "Warning: Latch display2\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA counter\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal counter\[4\]" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "display2\[1\]\$latch " "Warning: Latch display2\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA counter\[4\] " "Warning: Ports D and ENA on the latch are fed by the same signal counter\[4\]" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "display2\[2\]\$latch " "Warning: Latch display2\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA counter\[3\] " "Warning: Ports D and ENA on the latch are fed by the same signal counter\[3\]" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "display2\[3\]\$latch " "Warning: Latch display2\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA counter\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal counter\[2\]" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "display2\[4\]\$latch " "Warning: Latch display2\[4\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA counter\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal counter\[5\]" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "display2\[5\]\$latch " "Warning: Latch display2\[5\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA counter\[5\] " "Warning: Ports D and ENA on the latch are fed by the same signal counter\[5\]" {  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 9 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0 0}  } { { "watch.v" "" { Text "E:/quartus project/procedure/watch/watch.v" 27 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "74 " "Info: Implemented 74 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "14 " "Info: Implemented 14 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "58 " "Info: Implemented 58 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 15 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Peak virtual memory: 170 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 21:05:23 2008 " "Info: Processing ended: Thu Nov 27 21:05:23 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}