prev_cmp_watch.tan.qmsg

基于quartus II软件 用verilog 语言描述的一个秒表

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "counter\[0\] display2\[1\]\$latch clk 2.877 ns " "Info: Found hold time violation between source  pin or register \"counter\[0\]\" and destination pin or register \"display2\[1\]\$latch\" for clock \"clk\" (Hold time is 2.877 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.543 ns + Largest " "Info: + Largest clock skew is 4.543 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 6.889 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 6.889 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.787 ns) 2.664 ns counter\[4\] 2 REG LCFF_X10_Y5_N21 20 " "Info: 2: + IC(0.898 ns) + CELL(0.787 ns) = 2.664 ns; Loc. = LCFF_X10_Y5_N21; Fanout = 20; REG Node = 'counter\[4\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.685 ns" { clk counter[4] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(0.438 ns) 4.425 ns display1\[6\]~455 3 COMB LCCOMB_X18_Y6_N24 4 " "Info: 3: + IC(1.323 ns) + CELL(0.438 ns) = 4.425 ns; Loc. = LCCOMB_X18_Y6_N24; Fanout = 4; COMB Node = 'display1\[6\]~455'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.761 ns" { counter[4] display1[6]~455 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.270 ns) + CELL(0.000 ns) 5.695 ns display1\[6\]~455clkctrl 4 COMB CLKCTRL_G0 6 " "Info: 4: + IC(1.270 ns) + CELL(0.000 ns) = 5.695 ns; Loc. = CLKCTRL_G0; Fanout = 6; COMB Node = 'display1\[6\]~455clkctrl'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.270 ns" { display1[6]~455 display1[6]~455clkctrl } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.150 ns) 6.889 ns display2\[1\]\$latch 5 REG LCCOMB_X12_Y5_N22 1 " "Info: 5: + IC(1.044 ns) + CELL(0.150 ns) = 6.889 ns; Loc. = LCCOMB_X12_Y5_N22; Fanout = 1; REG Node = 'display2\[1\]\$latch'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.194 ns" { display1[6]~455clkctrl display2[1]$latch } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.354 ns ( 34.17 % ) " "Info: Total cell delay = 2.354 ns ( 34.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.535 ns ( 65.83 % ) " "Info: Total interconnect delay = 4.535 ns ( 65.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.889 ns" { clk counter[4] display1[6]~455 display1[6]~455clkctrl display2[1]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.889 ns" { clk {} clk~combout {} counter[4] {} display1[6]~455 {} display1[6]~455clkctrl {} display2[1]$latch {} } { 0.000ns 0.000ns 0.898ns 1.323ns 1.270ns 1.044ns } { 0.000ns 0.979ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.346 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.537 ns) 2.346 ns counter\[0\] 3 REG LCFF_X12_Y5_N11 10 " "Info: 3: + IC(0.708 ns) + CELL(0.537 ns) = 2.346 ns; Loc. = LCFF_X12_Y5_N11; Fanout = 10; REG Node = 'counter\[0\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.245 ns" { clk~clkctrl counter[0] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.62 % ) " "Info: Total cell delay = 1.516 ns ( 64.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.830 ns ( 35.38 % ) " "Info: Total interconnect delay = 0.830 ns ( 35.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { clk {} clk~combout {} clk~clkctrl {} counter[0] {} } { 0.000ns 0.000ns 0.122ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.889 ns" { clk counter[4] display1[6]~455 display1[6]~455clkctrl display2[1]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.889 ns" { clk {} clk~combout {} counter[4] {} display1[6]~455 {} display1[6]~455clkctrl {} display2[1]$latch {} } { 0.000ns 0.000ns 0.898ns 1.323ns 1.270ns 1.044ns } { 0.000ns 0.979ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { clk {} clk~combout {} clk~clkctrl {} counter[0] {} } { 0.000ns 0.000ns 0.122ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.416 ns - Shortest register register " "Info: - Shortest register to register delay is 1.416 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LCFF_X12_Y5_N11 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y5_N11; Fanout = 10; REG Node = 'counter\[0\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[0] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.346 ns) + CELL(0.398 ns) 0.744 ns WideOr12~180 2 COMB LCCOMB_X12_Y5_N28 1 " "Info: 2: + IC(0.346 ns) + CELL(0.398 ns) = 0.744 ns; Loc. = LCCOMB_X12_Y5_N28; Fanout = 1; COMB Node = 'WideOr12~180'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.744 ns" { counter[0] WideOr12~180 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.419 ns) 1.416 ns display2\[1\]\$latch 3 REG LCCOMB_X12_Y5_N22 1 " "Info: 3: + IC(0.253 ns) + CELL(0.419 ns) = 1.416 ns; Loc. = LCCOMB_X12_Y5_N22; Fanout = 1; REG Node = 'display2\[1\]\$latch'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.672 ns" { WideOr12~180 display2[1]$latch } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.817 ns ( 57.70 % ) " "Info: Total cell delay = 0.817 ns ( 57.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.599 ns ( 42.30 % ) " "Info: Total interconnect delay = 0.599 ns ( 42.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.416 ns" { counter[0] WideOr12~180 display2[1]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.416 ns" { counter[0] {} WideOr12~180 {} display2[1]$latch {} } { 0.000ns 0.346ns 0.253ns } { 0.000ns 0.398ns 0.419ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.889 ns" { clk counter[4] display1[6]~455 display1[6]~455clkctrl display2[1]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.889 ns" { clk {} clk~combout {} counter[4] {} display1[6]~455 {} display1[6]~455clkctrl {} display2[1]$latch {} } { 0.000ns 0.000ns 0.898ns 1.323ns 1.270ns 1.044ns } { 0.000ns 0.979ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { clk {} clk~combout {} clk~clkctrl {} counter[0] {} } { 0.000ns 0.000ns 0.122ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.416 ns" { counter[0] WideOr12~180 display2[1]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.416 ns" { counter[0] {} WideOr12~180 {} display2[1]$latch {} } { 0.000ns 0.346ns 0.253ns } { 0.000ns 0.398ns 0.419ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk display2\[2\] display2\[2\]\$latch 11.697 ns register " "Info: tco from clock \"clk\" to destination pin \"display2\[2\]\" through register \"display2\[2\]\$latch\" is 11.697 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.861 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.861 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.787 ns) 2.664 ns counter\[4\] 2 REG LCFF_X10_Y5_N21 20 " "Info: 2: + IC(0.898 ns) + CELL(0.787 ns) = 2.664 ns; Loc. = LCFF_X10_Y5_N21; Fanout = 20; REG Node = 'counter\[4\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.685 ns" { clk counter[4] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.323 ns) + CELL(0.438 ns) 4.425 ns display1\[6\]~455 3 COMB LCCOMB_X18_Y6_N24 4 " "Info: 3: + IC(1.323 ns) + CELL(0.438 ns) = 4.425 ns; Loc. = LCCOMB_X18_Y6_N24; Fanout = 4; COMB Node = 'display1\[6\]~455'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.761 ns" { counter[4] display1[6]~455 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.270 ns) + CELL(0.000 ns) 5.695 ns display1\[6\]~455clkctrl 4 COMB CLKCTRL_G0 6 " "Info: 4: + IC(1.270 ns) + CELL(0.000 ns) = 5.695 ns; Loc. = CLKCTRL_G0; Fanout = 6; COMB Node = 'display1\[6\]~455clkctrl'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.270 ns" { display1[6]~455 display1[6]~455clkctrl } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.016 ns) + CELL(0.150 ns) 6.861 ns display2\[2\]\$latch 5 REG LCCOMB_X18_Y6_N6 1 " "Info: 5: + IC(1.016 ns) + CELL(0.150 ns) = 6.861 ns; Loc. = LCCOMB_X18_Y6_N6; Fanout = 1; REG Node = 'display2\[2\]\$latch'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.166 ns" { display1[6]~455clkctrl display2[2]$latch } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.354 ns ( 34.31 % ) " "Info: Total cell delay = 2.354 ns ( 34.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.507 ns ( 65.69 % ) " "Info: Total interconnect delay = 4.507 ns ( 65.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.861 ns" { clk counter[4] display1[6]~455 display1[6]~455clkctrl display2[2]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.861 ns" { clk {} clk~combout {} counter[4] {} display1[6]~455 {} display1[6]~455clkctrl {} display2[2]$latch {} } { 0.000ns 0.000ns 0.898ns 1.323ns 1.270ns 1.016ns } { 0.000ns 0.979ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.836 ns + Longest register pin " "Info: + Longest register to pin delay is 4.836 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns display2\[2\]\$latch 1 REG LCCOMB_X18_Y6_N6 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X18_Y6_N6; Fanout = 1; REG Node = 'display2\[2\]\$latch'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { display2[2]$latch } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.088 ns) + CELL(2.748 ns) 4.836 ns display2\[2\] 2 PIN PIN_F6 0 " "Info: 2: + IC(2.088 ns) + CELL(2.748 ns) = 4.836 ns; Loc. = PIN_F6; Fanout = 0; PIN Node = 'display2\[2\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.836 ns" { display2[2]$latch display2[2] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.748 ns ( 56.82 % ) " "Info: Total cell delay = 2.748 ns ( 56.82 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.088 ns ( 43.18 % ) " "Info: Total interconnect delay = 2.088 ns ( 43.18 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.836 ns" { display2[2]$latch display2[2] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.836 ns" { display2[2]$latch {} display2[2] {} } { 0.000ns 2.088ns } { 0.000ns 2.748ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.861 ns" { clk counter[4] display1[6]~455 display1[6]~455clkctrl display2[2]$latch } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.861 ns" { clk {} clk~combout {} counter[4] {} display1[6]~455 {} display1[6]~455clkctrl {} display2[2]$latch {} } { 0.000ns 0.000ns 0.898ns 1.323ns 1.270ns 1.016ns } { 0.000ns 0.979ns 0.787ns 0.438ns 0.000ns 0.150ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.836 ns" { display2[2]$latch display2[2] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "4.836 ns" { display2[2]$latch {} display2[2] {} } { 0.000ns 2.088ns } { 0.000ns 2.748ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 17 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 17 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "127 " "Info: Peak virtual memory: 127 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 24 19:15:43 2008 " "Info: Processing ended: Fri Oct 24 19:15:43 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}