prev_cmp_watch.tan.qmsg

基于quartus II软件 用verilog 语言描述的一个秒表

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "display1\[6\]~455 " "Info: Detected gated clock \"display1\[6\]~455\" as buffer" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "display1\[6\]~455" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter\[2\] " "Info: Detected ripple clock \"counter\[2\]\" as buffer" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter\[3\] " "Info: Detected ripple clock \"counter\[3\]\" as buffer" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter\[4\] " "Info: Detected ripple clock \"counter\[4\]\" as buffer" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "counter\[5\] " "Info: Detected ripple clock \"counter\[5\]\" as buffer" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } } { "f:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "f:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "counter\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register counter\[0\] counter\[5\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"counter\[0\]\" and destination register \"counter\[5\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.979 ns + Longest register register " "Info: + Longest register to register delay is 1.979 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns counter\[0\] 1 REG LCFF_X12_Y5_N11 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y5_N11; Fanout = 10; REG Node = 'counter\[0\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[0] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.768 ns) + CELL(0.504 ns) 1.272 ns counter\[1\]~215 2 COMB LCCOMB_X10_Y5_N14 2 " "Info: 2: + IC(0.768 ns) + CELL(0.504 ns) = 1.272 ns; Loc. = LCCOMB_X10_Y5_N14; Fanout = 2; COMB Node = 'counter\[1\]~215'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.272 ns" { counter[0] counter[1]~215 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.343 ns counter\[2\]~217 3 COMB LCCOMB_X10_Y5_N16 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 1.343 ns; Loc. = LCCOMB_X10_Y5_N16; Fanout = 2; COMB Node = 'counter\[2\]~217'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { counter[1]~215 counter[2]~217 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.414 ns counter\[3\]~219 4 COMB LCCOMB_X10_Y5_N18 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.414 ns; Loc. = LCCOMB_X10_Y5_N18; Fanout = 2; COMB Node = 'counter\[3\]~219'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { counter[2]~217 counter[3]~219 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.485 ns counter\[4\]~221 5 COMB LCCOMB_X10_Y5_N20 1 " "Info: 5: + IC(0.000 ns) + CELL(0.071 ns) = 1.485 ns; Loc. = LCCOMB_X10_Y5_N20; Fanout = 1; COMB Node = 'counter\[4\]~221'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.071 ns" { counter[3]~219 counter[4]~221 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.895 ns counter\[5\]~222 6 COMB LCCOMB_X10_Y5_N22 1 " "Info: 6: + IC(0.000 ns) + CELL(0.410 ns) = 1.895 ns; Loc. = LCCOMB_X10_Y5_N22; Fanout = 1; COMB Node = 'counter\[5\]~222'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { counter[4]~221 counter[5]~222 } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.979 ns counter\[5\] 7 REG LCFF_X10_Y5_N23 25 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 1.979 ns; Loc. = LCFF_X10_Y5_N23; Fanout = 25; REG Node = 'counter\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { counter[5]~222 counter[5] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.211 ns ( 61.19 % ) " "Info: Total cell delay = 1.211 ns ( 61.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.768 ns ( 38.81 % ) " "Info: Total interconnect delay = 0.768 ns ( 38.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.979 ns" { counter[0] counter[1]~215 counter[2]~217 counter[3]~219 counter[4]~221 counter[5]~222 counter[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.979 ns" { counter[0] {} counter[1]~215 {} counter[2]~217 {} counter[3]~219 {} counter[4]~221 {} counter[5]~222 {} counter[5] {} } { 0.000ns 0.768ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.504ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.068 ns - Smallest " "Info: - Smallest clock skew is 0.068 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.414 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.414 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.898 ns) + CELL(0.537 ns) 2.414 ns counter\[5\] 2 REG LCFF_X10_Y5_N23 25 " "Info: 2: + IC(0.898 ns) + CELL(0.537 ns) = 2.414 ns; Loc. = LCFF_X10_Y5_N23; Fanout = 25; REG Node = 'counter\[5\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.435 ns" { clk counter[5] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 62.80 % ) " "Info: Total cell delay = 1.516 ns ( 62.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.898 ns ( 37.20 % ) " "Info: Total interconnect delay = 0.898 ns ( 37.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.414 ns" { clk counter[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.414 ns" { clk {} clk~combout {} counter[5] {} } { 0.000ns 0.000ns 0.898ns } { 0.000ns 0.979ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.346 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns clk 1 CLK PIN_H2 5 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 5; CLK Node = 'clk'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns clk~clkctrl 2 COMB CLKCTRL_G2 2 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 2; COMB Node = 'clk~clkctrl'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.708 ns) + CELL(0.537 ns) 2.346 ns counter\[0\] 3 REG LCFF_X12_Y5_N11 10 " "Info: 3: + IC(0.708 ns) + CELL(0.537 ns) = 2.346 ns; Loc. = LCFF_X12_Y5_N11; Fanout = 10; REG Node = 'counter\[0\]'" {  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.245 ns" { clk~clkctrl counter[0] } "NODE_NAME" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.62 % ) " "Info: Total cell delay = 1.516 ns ( 64.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.830 ns ( 35.38 % ) " "Info: Total interconnect delay = 0.830 ns ( 35.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { clk {} clk~combout {} clk~clkctrl {} counter[0] {} } { 0.000ns 0.000ns 0.122ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.414 ns" { clk counter[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.414 ns" { clk {} clk~combout {} counter[5] {} } { 0.000ns 0.000ns 0.898ns } { 0.000ns 0.979ns 0.537ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { clk {} clk~combout {} clk~clkctrl {} counter[0] {} } { 0.000ns 0.000ns 0.122ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.979 ns" { counter[0] counter[1]~215 counter[2]~217 counter[3]~219 counter[4]~221 counter[5]~222 counter[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "1.979 ns" { counter[0] {} counter[1]~215 {} counter[2]~217 {} counter[3]~219 {} counter[4]~221 {} counter[5]~222 {} counter[5] {} } { 0.000ns 0.768ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.504ns 0.071ns 0.071ns 0.071ns 0.410ns 0.084ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.414 ns" { clk counter[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.414 ns" { clk {} clk~combout {} counter[5] {} } { 0.000ns 0.000ns 0.898ns } { 0.000ns 0.979ns 0.537ns } "" } } { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.346 ns" { clk clk~clkctrl counter[0] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.346 ns" { clk {} clk~combout {} clk~clkctrl {} counter[0] {} } { 0.000ns 0.000ns 0.122ns 0.708ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "f:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { counter[5] } "NODE_NAME" } } { "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "f:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { counter[5] {} } {  } {  } "" } } { "watch.v" "" { Text "I:/工作/watch/watch.v" 9 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 36 " "Warning: Circuit may not operate. Detected 36 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}