prev_cmp_watch.tan.qmsg

基于quartus II软件 用verilog 语言描述的一个秒表

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Oct 24 19:15:34 2008 " "Info: Processing started: Fri Oct 24 19:15:34 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off watch -c watch --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off watch -c watch --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[0\]\$latch " "Warning: Node \"display1\[0\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[1\]\$latch " "Warning: Node \"display1\[1\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[2\]\$latch " "Warning: Node \"display1\[2\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[3\]\$latch " "Warning: Node \"display1\[3\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[4\]\$latch " "Warning: Node \"display1\[4\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[5\]\$latch " "Warning: Node \"display1\[5\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display1\[6\]\$latch " "Warning: Node \"display1\[6\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 15 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display2\[0\]\$latch " "Warning: Node \"display2\[0\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display2\[1\]\$latch " "Warning: Node \"display2\[1\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display2\[2\]\$latch " "Warning: Node \"display2\[2\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display2\[3\]\$latch " "Warning: Node \"display2\[3\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display2\[4\]\$latch " "Warning: Node \"display2\[4\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "display2\[5\]\$latch " "Warning: Node \"display2\[5\]\$latch\" is a latch" {  } { { "watch.v" "" { Text "I:/工作/watch/watch.v" 25 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}