watch.v

基于quartus II软件 用verilog 语言描述的一个秒表

module watch(clk,rst,display1,display2);
input   clk,rst;
output  [6:0] display1,display2;
reg [5:0] counter;
reg [6:0] display1,display2;

always@(posedge clk or negedge rst)
 if(!rst) counter<=0;
  else if(counter>59) counter<=0;
     else
  counter<=counter+1'b1;

always@(counter)

begin if(counter<10) display1=7'b1110111;
else
 if(counter<20)  display1=7'b1101101;
else
if(counter<30) display1=7'b0100010;
else
if(counter<40) display1=7'b0100100;
else
if(counter<50) display1=7'b1000101;
else
if(counter<60) display1=7'b0010100;
 end
always@(counter)
case(counter)
0,10,20,30,40,50:   display2=7'b1110111;
1,11,21,31,41,51:   display2=7'b1101101;
2,12,22,32,42,52:   display2=7'b0100010;
3,13,23,33,43,53:   display2=7'b0100100;
4,14,24,34,44,54:   display2=7'b1000101;
5,15,25,35,45,55:   display2=7'b0010100;
6,16,26,36,46,56:   display2=7'b0010000;
7,17,27,37,47,57:   display2=7'b0101100;
8,18,28,38,48,58:   display2=7'b0000000;
9,19,29,39,49,59:   display2=7'b0000100;
endcase 
endmodule