watch.tan.rpt

基于quartus II软件 用verilog 语言描述的一个秒表

+-------+--------------+------------+-------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Thu Nov 27 21:26:45 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off watch -c watch --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "display1[0]$latch" is a latch
    Warning: Node "display1[1]$latch" is a latch
    Warning: Node "display1[2]$latch" is a latch
    Warning: Node "display1[3]$latch" is a latch
    Warning: Node "display1[4]$latch" is a latch
    Warning: Node "display1[5]$latch" is a latch
    Warning: Node "display1[6]$latch" is a latch
    Warning: Node "display2[0]$latch" is a latch
    Warning: Node "display2[1]$latch" is a latch
    Warning: Node "display2[2]$latch" is a latch
    Warning: Node "display2[3]$latch" is a latch
    Warning: Node "display2[4]$latch" is a latch
    Warning: Node "display2[5]$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "counter[2]" as buffer
    Info: Detected ripple clock "counter[3]" as buffer
    Info: Detected ripple clock "counter[4]" as buffer
    Info: Detected gated clock "display1[6]~524" as buffer
    Info: Detected ripple clock "counter[5]" as buffer
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "counter[4]" and destination register "counter[1]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.529 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y22_N21; Fanout = 20; REG Node = 'counter[4]'
            Info: 2: + IC(0.347 ns) + CELL(0.410 ns) = 0.757 ns; Loc. = LCCOMB_X34_Y22_N8; Fanout = 10; COMB Node = 'display1[6]~524'
            Info: 3: + IC(0.262 ns) + CELL(0.510 ns) = 1.529 ns; Loc. = LCFF_X34_Y22_N15; Fanout = 19; REG Node = 'counter[1]'
            Info: Total cell delay = 0.920 ns ( 60.17 % )
            Info: Total interconnect delay = 0.609 ns ( 39.83 % )
        Info: - Smallest clock skew is -0.339 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.661 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.007 ns) + CELL(0.537 ns) = 2.661 ns; Loc. = LCFF_X34_Y22_N15; Fanout = 19; REG Node = 'counter[1]'
                Info: Total cell delay = 1.536 ns ( 57.72 % )
                Info: Total interconnect delay = 1.125 ns ( 42.28 % )
            Info: - Longest clock path from clock "clk" to source register is 3.000 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 5; CLK Node = 'clk'
                Info: 2: + IC(1.464 ns) + CELL(0.537 ns) = 3.000 ns; Loc. = LCFF_X34_Y22_N21; Fanout = 20; REG Node = 'counter[4]'
                Info: Total cell delay = 1.536 ns ( 51.20 % )
                Info: Total interconnect delay = 1.464 ns ( 48.80 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Warning: Circuit may not operate. Detected 36 non-operational path(s) clocked by clock "clk" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "counter[0]" and destination pin or register "display2[4]$latch" for clock "clk" (Hold time is 2.71 ns)
    Info: + Largest clock skew is 4.299 ns
        Info: + Longest clock path from clock "clk" to destination register is 6.960 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(1.464 ns) + CELL(0.787 ns) = 3.250 ns; Loc. = LCFF_X34_Y22_N21; Fanout = 20; REG Node = 'counter[4]'
            Info: 3: + IC(0.347 ns) + CELL(0.410 ns) = 4.007 ns; Loc. = LCCOMB_X34_Y22_N8; Fanout = 10; COMB Node = 'display1[6]~524'
            Info: 4: + IC(1.465 ns) + CELL(0.000 ns) = 5.472 ns; Loc. = CLKCTRL_G11; Fanout = 6; COMB Node = 'display1[6]~524clkctrl'
            Info: 5: + IC(1.338 ns) + CELL(0.150 ns) = 6.960 ns; Loc. = LCCOMB_X34_Y22_N30; Fanout = 1; REG Node = 'display2[4]$latch'
            Info: Total cell delay = 2.346 ns ( 33.71 % )
            Info: Total interconnect delay = 4.614 ns ( 66.29 % )
        Info: - Shortest clock path from clock "clk" to source register is 2.661 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 5; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 2; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.007 ns) + CELL(0.537 ns) = 2.661 ns; Loc. = LCFF_X34_Y22_N13; Fanout = 9; REG Node = 'counter[0]'
            Info: Total cell delay = 1.536 ns ( 57.72 % )
            Info: Total interconnect delay = 1.125 ns ( 42.28 % )
    Info: - Micro clock to output delay of source is 0.250 ns
    Info: - Shortest register to register delay is 1.339 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y22_N13; Fanout = 9; REG Node = 'counter[0]'
        Info: 2: + IC(0.525 ns) + CELL(0.275 ns) = 0.800 ns; Loc. = LCCOMB_X34_Y22_N24; Fanout = 1; COMB Node = 'WideOr6~265'
        Info: 3: + IC(0.264 ns) + CELL(0.275 ns) = 1.339 ns; Loc. = LCCOMB_X34_Y22_N30; Fanout = 1; REG Node = 'display2[4]$latch'
        Info: Total cell delay = 0.550 ns ( 41.08 % )
        Info: Total interconnect delay = 0.789 ns ( 58.92 % )
    Info: + Micro hold delay of destination is 0.000 ns
Info: tco from clock "clk" to destination pin "display2[6]" through register "display2[0]$latch" is 11.681 ns
    Info: + Longest clock path from clock "clk" to source register is 6.971 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 5; CLK Node = 'clk'
        Info: 2: + IC(1.464 ns) + CELL(0.787 ns) = 3.250 ns; Loc. = LCFF_X34_Y22_N21; Fanout = 20; REG Node = 'counter[4]'
        Info: 3: + IC(0.347 ns) + CELL(0.410 ns) = 4.007 ns; Loc. = LCCOMB_X34_Y22_N8; Fanout = 10; COMB Node = 'display1[6]~524'
        Info: 4: + IC(1.465 ns) + CELL(0.000 ns) = 5.472 ns; Loc. = CLKCTRL_G11; Fanout = 6; COMB Node = 'display1[6]~524clkctrl'
        Info: 5: + IC(1.349 ns) + CELL(0.150 ns) = 6.971 ns; Loc. = LCCOMB_X32_Y19_N8; Fanout = 2; REG Node = 'display2[0]$latch'
        Info: Total cell delay = 2.346 ns ( 33.65 % )
        Info: Total interconnect delay = 4.625 ns ( 66.35 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 4.710 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X32_Y19_N8; Fanout = 2; REG Node = 'display2[0]$latch'
        Info: 2: + IC(1.912 ns) + CELL(2.798 ns) = 4.710 ns; Loc. = PIN_AE12; Fanout = 0; PIN Node = 'display2[6]'
        Info: Total cell delay = 2.798 ns ( 59.41 % )
        Info: Total interconnect delay = 1.912 ns ( 40.59 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 17 warnings
    Info: Peak virtual memory: 136 megabytes
    Info: Processing ended: Thu Nov 27 21:26:47 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01