📄 aaa3_8.tan.rpt
字号:
Classic Timing Analyzer report for aaa3_8
Tue Oct 14 16:25:26 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+-------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+-------+--------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 12.777 ns ; in[1] ; out[2] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+-------+--------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+--------------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+-------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+-------+--------+
; N/A ; None ; 12.777 ns ; in[1] ; out[2] ;
; N/A ; None ; 12.642 ns ; in[1] ; out[5] ;
; N/A ; None ; 12.076 ns ; in[1] ; out[3] ;
; N/A ; None ; 11.787 ns ; in[1] ; out[4] ;
; N/A ; None ; 11.785 ns ; in[1] ; out[7] ;
; N/A ; None ; 11.764 ns ; in[1] ; out[1] ;
; N/A ; None ; 11.751 ns ; in[1] ; out[0] ;
; N/A ; None ; 11.286 ns ; in[1] ; out[6] ;
; N/A ; None ; 8.859 ns ; in[2] ; out[2] ;
; N/A ; None ; 8.664 ns ; in[2] ; out[5] ;
; N/A ; None ; 8.588 ns ; in[0] ; out[2] ;
; N/A ; None ; 8.450 ns ; in[0] ; out[5] ;
; N/A ; None ; 8.114 ns ; in[2] ; out[3] ;
; N/A ; None ; 7.890 ns ; in[0] ; out[3] ;
; N/A ; None ; 7.871 ns ; in[2] ; out[4] ;
; N/A ; None ; 7.818 ns ; in[2] ; out[1] ;
; N/A ; None ; 7.813 ns ; in[2] ; out[7] ;
; N/A ; None ; 7.797 ns ; in[2] ; out[0] ;
; N/A ; None ; 7.599 ns ; in[0] ; out[4] ;
; N/A ; None ; 7.592 ns ; in[0] ; out[7] ;
; N/A ; None ; 7.578 ns ; in[0] ; out[1] ;
; N/A ; None ; 7.558 ns ; in[0] ; out[0] ;
; N/A ; None ; 7.331 ns ; in[2] ; out[6] ;
; N/A ; None ; 7.101 ns ; in[0] ; out[6] ;
+-------+-------------------+-----------------+-------+--------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Tue Oct 14 16:25:26 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off aaa3_8 -c aaa3_8 --timing_analysis_only
Info: Longest tpd from source pin "in[1]" to destination pin "out[2]" is 12.777 ns
Info: 1: + IC(0.000 ns) + CELL(0.832 ns) = 0.832 ns; Loc. = PIN_M5; Fanout = 8; PIN Node = 'in[1]'
Info: 2: + IC(5.950 ns) + CELL(0.150 ns) = 6.932 ns; Loc. = LCCOMB_X27_Y16_N12; Fanout = 1; COMB Node = 'Decoder0~71'
Info: 3: + IC(3.037 ns) + CELL(2.808 ns) = 12.777 ns; Loc. = PIN_A6; Fanout = 0; PIN Node = 'out[2]'
Info: Total cell delay = 3.790 ns ( 29.66 % )
Info: Total interconnect delay = 8.987 ns ( 70.34 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 115 megabytes of memory during processing
Info: Processing ended: Tue Oct 14 16:25:27 2008
Info: Elapsed time: 00:00:01
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -