aaa3_8.map.summary

来自「基于quartus II软件 用verilog 语言描述的38译码器」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Tue Oct 14 16:25:05 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : aaa3_8
Top-level Entity Name : aaa3_8
Family : Cyclone II
Total logic elements : 8
    Total combinational functions : 8
    Dedicated logic registers : 0
Total registers : 0
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0