dk74x191.tan.qmsg

基于quartus II软件 用verilog语言描述的74ls191

{ "Info" "ITDB_FULL_TPD_RESULT" "din\[4\] dout\[4\] 12.188 ns Longest " "Info: Longest tpd from source pin \"din\[4\]\" to destination pin \"dout\[4\]\" is 12.188 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns din\[4\] 1 PIN PIN_G16 2 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_G16; Fanout = 2; PIN Node = 'din\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[4] } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.054 ns) + CELL(0.438 ns) 6.302 ns dout\[4\]~reg0head_lut 2 COMB LCCOMB_X40_Y35_N22 4 " "Info: 2: + IC(5.054 ns) + CELL(0.438 ns) = 6.302 ns; Loc. = LCCOMB_X40_Y35_N22; Fanout = 4; COMB Node = 'dout\[4\]~reg0head_lut'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.492 ns" { din[4] dout[4]~reg0head_lut } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.118 ns) + CELL(2.768 ns) 12.188 ns dout\[4\] 3 PIN PIN_AC15 0 " "Info: 3: + IC(3.118 ns) + CELL(2.768 ns) = 12.188 ns; Loc. = PIN_AC15; Fanout = 0; PIN Node = 'dout\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.886 ns" { dout[4]~reg0head_lut dout[4] } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.016 ns ( 32.95 % ) " "Info: Total cell delay = 4.016 ns ( 32.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.172 ns ( 67.05 % ) " "Info: Total interconnect delay = 8.172 ns ( 67.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.188 ns" { din[4] dout[4]~reg0head_lut dout[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.188 ns" { din[4] {} din[4]~combout {} dout[4]~reg0head_lut {} dout[4] {} } { 0.000ns 0.000ns 5.054ns 3.118ns } { 0.000ns 0.810ns 0.438ns 2.768ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "dout\[0\]~reg0latch din\[0\] ld_n 0.071 ns register " "Info: th for register \"dout\[0\]~reg0latch\" (data pin = \"din\[0\]\", clock pin = \"ld_n\") is 0.071 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ld_n destination 2.603 ns + Longest register " "Info: + Longest clock path from clock \"ld_n\" to destination register is 2.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns ld_n 1 CLK PIN_P1 9 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 9; CLK Node = 'ld_n'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { ld_n } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.113 ns) + CELL(0.000 ns) 1.112 ns ld_n~clkctrl 2 COMB CLKCTRL_G1 16 " "Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'ld_n~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.113 ns" { ld_n ld_n~clkctrl } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.341 ns) + CELL(0.150 ns) 2.603 ns dout\[0\]~reg0latch 3 REG LCCOMB_X38_Y35_N0 2 " "Info: 3: + IC(1.341 ns) + CELL(0.150 ns) = 2.603 ns; Loc. = LCCOMB_X38_Y35_N0; Fanout = 2; REG Node = 'dout\[0\]~reg0latch'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.491 ns" { ld_n~clkctrl dout[0]~reg0latch } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.149 ns ( 44.14 % ) " "Info: Total cell delay = 1.149 ns ( 44.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.454 ns ( 55.86 % ) " "Info: Total interconnect delay = 1.454 ns ( 55.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.603 ns" { ld_n ld_n~clkctrl dout[0]~reg0latch } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.603 ns" { ld_n {} ld_n~combout {} ld_n~clkctrl {} dout[0]~reg0latch {} } { 0.000ns 0.000ns 0.113ns 1.341ns } { 0.000ns 0.999ns 0.000ns 0.150ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.532 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.532 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns din\[0\] 1 PIN PIN_D13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 2; PIN Node = 'din\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[0] } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.115 ns) + CELL(0.438 ns) 2.532 ns dout\[0\]~reg0latch 2 REG LCCOMB_X38_Y35_N0 2 " "Info: 2: + IC(1.115 ns) + CELL(0.438 ns) = 2.532 ns; Loc. = LCCOMB_X38_Y35_N0; Fanout = 2; REG Node = 'dout\[0\]~reg0latch'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.553 ns" { din[0] dout[0]~reg0latch } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.417 ns ( 55.96 % ) " "Info: Total cell delay = 1.417 ns ( 55.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.115 ns ( 44.04 % ) " "Info: Total interconnect delay = 1.115 ns ( 44.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.532 ns" { din[0] dout[0]~reg0latch } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.532 ns" { din[0] {} din[0]~combout {} dout[0]~reg0latch {} } { 0.000ns 0.000ns 1.115ns } { 0.000ns 0.979ns 0.438ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.603 ns" { ld_n ld_n~clkctrl dout[0]~reg0latch } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.603 ns" { ld_n {} ld_n~combout {} ld_n~clkctrl {} dout[0]~reg0latch {} } { 0.000ns 0.000ns 0.113ns 1.341ns } { 0.000ns 0.999ns 0.000ns 0.150ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.532 ns" { din[0] dout[0]~reg0latch } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.532 ns" { din[0] {} din[0]~combout {} dout[0]~reg0latch {} } { 0.000ns 0.000ns 1.115ns } { 0.000ns 0.979ns 0.438ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 10 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Dec 22 15:34:06 2008 " "Info: Processing ended: Mon Dec 22 15:34:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}