prev_cmp_dk74x191.tan.qmsg

基于quartus II软件 用verilog语言描述的74ls191

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "ld_n " "Info: Assuming node \"ld_n\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register dout\[2\]~reg0_emulated register dout\[4\]~reg0_emulated 343.52 MHz 2.911 ns Internal " "Info: Clock \"clk\" has Internal fmax of 343.52 MHz between source register \"dout\[2\]~reg0_emulated\" and destination register \"dout\[4\]~reg0_emulated\" (period= 2.911 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.695 ns + Longest register register " "Info: + Longest register to register delay is 2.695 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[2\]~reg0_emulated 1 REG LCFF_X42_Y35_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y35_N25; Fanout = 1; REG Node = 'dout\[2\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout[2]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.491 ns) + CELL(0.150 ns) 0.641 ns dout\[2\]~reg0head_lut 2 COMB LCCOMB_X41_Y35_N24 4 " "Info: 2: + IC(0.491 ns) + CELL(0.150 ns) = 0.641 ns; Loc. = LCCOMB_X41_Y35_N24; Fanout = 4; COMB Node = 'dout\[2\]~reg0head_lut'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.641 ns" { dout[2]~reg0_emulated dout[2]~reg0head_lut } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.271 ns) + CELL(0.414 ns) 1.326 ns Add1~150 3 COMB LCCOMB_X41_Y35_N12 2 " "Info: 3: + IC(0.271 ns) + CELL(0.414 ns) = 1.326 ns; Loc. = LCCOMB_X41_Y35_N12; Fanout = 2; COMB Node = 'Add1~150'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { dout[2]~reg0head_lut Add1~150 } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.485 ns Add1~152 4 COMB LCCOMB_X41_Y35_N14 2 " "Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 1.485 ns; Loc. = LCCOMB_X41_Y35_N14; Fanout = 2; COMB Node = 'Add1~152'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.159 ns" { Add1~150 Add1~152 } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 1.895 ns Add1~153 5 COMB LCCOMB_X41_Y35_N16 1 " "Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.895 ns; Loc. = LCCOMB_X41_Y35_N16; Fanout = 1; COMB Node = 'Add1~153'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add1~152 Add1~153 } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.275 ns) 2.611 ns dout\[4\]~reg0data_lut 6 COMB LCCOMB_X40_Y35_N12 1 " "Info: 6: + IC(0.441 ns) + CELL(0.275 ns) = 2.611 ns; Loc. = LCCOMB_X40_Y35_N12; Fanout = 1; COMB Node = 'dout\[4\]~reg0data_lut'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.716 ns" { Add1~153 dout[4]~reg0data_lut } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.695 ns dout\[4\]~reg0_emulated 7 REG LCFF_X40_Y35_N13 1 " "Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 2.695 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout\[4\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dout[4]~reg0data_lut dout[4]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.492 ns ( 55.36 % ) " "Info: Total cell delay = 1.492 ns ( 55.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.203 ns ( 44.64 % ) " "Info: Total interconnect delay = 1.203 ns ( 44.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { dout[2]~reg0_emulated dout[2]~reg0head_lut Add1~150 Add1~152 Add1~153 dout[4]~reg0data_lut dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { dout[2]~reg0_emulated {} dout[2]~reg0head_lut {} Add1~150 {} Add1~152 {} Add1~153 {} dout[4]~reg0data_lut {} dout[4]~reg0_emulated {} } { 0.000ns 0.491ns 0.271ns 0.000ns 0.000ns 0.441ns 0.000ns } { 0.000ns 0.150ns 0.414ns 0.159ns 0.410ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.002 ns - Smallest " "Info: - Smallest clock skew is -0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.682 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 2.682 ns dout\[4\]~reg0_emulated 3 REG LCFF_X40_Y35_N13 1 " "Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout\[4\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.27 % ) " "Info: Total cell delay = 1.536 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 42.73 % ) " "Info: Total interconnect delay = 1.146 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.684 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.684 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.030 ns) + CELL(0.537 ns) 2.684 ns dout\[2\]~reg0_emulated 3 REG LCFF_X42_Y35_N25 1 " "Info: 3: + IC(1.030 ns) + CELL(0.537 ns) = 2.684 ns; Loc. = LCFF_X42_Y35_N25; Fanout = 1; REG Node = 'dout\[2\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.567 ns" { clk~clkctrl dout[2]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.23 % ) " "Info: Total cell delay = 1.536 ns ( 57.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.148 ns ( 42.77 % ) " "Info: Total interconnect delay = 1.148 ns ( 42.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { clk clk~clkctrl dout[2]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { clk {} clk~combout {} clk~clkctrl {} dout[2]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { clk clk~clkctrl dout[2]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { clk {} clk~combout {} clk~clkctrl {} dout[2]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { dout[2]~reg0_emulated dout[2]~reg0head_lut Add1~150 Add1~152 Add1~153 dout[4]~reg0data_lut dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.695 ns" { dout[2]~reg0_emulated {} dout[2]~reg0head_lut {} Add1~150 {} Add1~152 {} Add1~153 {} dout[4]~reg0data_lut {} dout[4]~reg0_emulated {} } { 0.000ns 0.491ns 0.271ns 0.000ns 0.000ns 0.441ns 0.000ns } { 0.000ns 0.150ns 0.414ns 0.159ns 0.410ns 0.275ns 0.084ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.684 ns" { clk clk~clkctrl dout[2]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.684 ns" { clk {} clk~combout {} clk~clkctrl {} dout[2]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.030ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "dout\[4\]~reg0_emulated din\[3\] clk 6.516 ns register " "Info: tsu for register \"dout\[4\]~reg0_emulated\" (data pin = \"din\[3\]\", clock pin = \"clk\") is 6.516 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.234 ns + Longest pin register " "Info: + Longest pin to register delay is 9.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.820 ns) 0.820 ns din\[3\] 1 PIN PIN_AB15 2 " "Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_AB15; Fanout = 2; PIN Node = 'din\[3\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { din[3] } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.852 ns) + CELL(0.419 ns) 7.091 ns dout\[3\]~reg0head_lut 2 COMB LCCOMB_X40_Y35_N26 4 " "Info: 2: + IC(5.852 ns) + CELL(0.419 ns) = 7.091 ns; Loc. = LCCOMB_X40_Y35_N26; Fanout = 4; COMB Node = 'dout\[3\]~reg0head_lut'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.271 ns" { din[3] dout[3]~reg0head_lut } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.448 ns) + CELL(0.485 ns) 8.024 ns Add1~152 3 COMB LCCOMB_X41_Y35_N14 2 " "Info: 3: + IC(0.448 ns) + CELL(0.485 ns) = 8.024 ns; Loc. = LCCOMB_X41_Y35_N14; Fanout = 2; COMB Node = 'Add1~152'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.933 ns" { dout[3]~reg0head_lut Add1~152 } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 8.434 ns Add1~153 4 COMB LCCOMB_X41_Y35_N16 1 " "Info: 4: + IC(0.000 ns) + CELL(0.410 ns) = 8.434 ns; Loc. = LCCOMB_X41_Y35_N16; Fanout = 1; COMB Node = 'Add1~153'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.410 ns" { Add1~152 Add1~153 } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.441 ns) + CELL(0.275 ns) 9.150 ns dout\[4\]~reg0data_lut 5 COMB LCCOMB_X40_Y35_N12 1 " "Info: 5: + IC(0.441 ns) + CELL(0.275 ns) = 9.150 ns; Loc. = LCCOMB_X40_Y35_N12; Fanout = 1; COMB Node = 'dout\[4\]~reg0data_lut'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.716 ns" { Add1~153 dout[4]~reg0data_lut } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.234 ns dout\[4\]~reg0_emulated 6 REG LCFF_X40_Y35_N13 1 " "Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.234 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout\[4\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { dout[4]~reg0data_lut dout[4]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.493 ns ( 27.00 % ) " "Info: Total cell delay = 2.493 ns ( 27.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.741 ns ( 73.00 % ) " "Info: Total interconnect delay = 6.741 ns ( 73.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.234 ns" { din[3] dout[3]~reg0head_lut Add1~152 Add1~153 dout[4]~reg0data_lut dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.234 ns" { din[3] {} din[3]~combout {} dout[3]~reg0head_lut {} Add1~152 {} Add1~153 {} dout[4]~reg0data_lut {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 5.852ns 0.448ns 0.000ns 0.441ns 0.000ns } { 0.000ns 0.820ns 0.419ns 0.485ns 0.410ns 0.275ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.682 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 2.682 ns dout\[4\]~reg0_emulated 3 REG LCFF_X40_Y35_N13 1 " "Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout\[4\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.27 % ) " "Info: Total cell delay = 1.536 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 42.73 % ) " "Info: Total interconnect delay = 1.146 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.234 ns" { din[3] dout[3]~reg0head_lut Add1~152 Add1~153 dout[4]~reg0data_lut dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.234 ns" { din[3] {} din[3]~combout {} dout[3]~reg0head_lut {} Add1~152 {} Add1~153 {} dout[4]~reg0data_lut {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 5.852ns 0.448ns 0.000ns 0.441ns 0.000ns } { 0.000ns 0.820ns 0.419ns 0.485ns 0.410ns 0.275ns 0.084ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[4\] dout\[4\]~reg0_emulated 9.267 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[4\]\" through register \"dout\[4\]~reg0_emulated\" is 9.267 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.682 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.682 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G3 8 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(0.537 ns) 2.682 ns dout\[4\]~reg0_emulated 3 REG LCFF_X40_Y35_N13 1 " "Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout\[4\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.565 ns" { clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.27 % ) " "Info: Total cell delay = 1.536 ns ( 57.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 42.73 % ) " "Info: Total interconnect delay = 1.146 ns ( 42.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.335 ns + Longest register pin " "Info: + Longest register to pin delay is 6.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout\[4\]~reg0_emulated 1 REG LCFF_X40_Y35_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout\[4\]~reg0_emulated'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout[4]~reg0_emulated } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.299 ns) + CELL(0.150 ns) 0.449 ns dout\[4\]~reg0head_lut 2 COMB LCCOMB_X40_Y35_N22 4 " "Info: 2: + IC(0.299 ns) + CELL(0.150 ns) = 0.449 ns; Loc. = LCCOMB_X40_Y35_N22; Fanout = 4; COMB Node = 'dout\[4\]~reg0head_lut'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "0.449 ns" { dout[4]~reg0_emulated dout[4]~reg0head_lut } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.118 ns) + CELL(2.768 ns) 6.335 ns dout\[4\] 3 PIN PIN_AC15 0 " "Info: 3: + IC(3.118 ns) + CELL(2.768 ns) = 6.335 ns; Loc. = PIN_AC15; Fanout = 0; PIN Node = 'dout\[4\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.886 ns" { dout[4]~reg0head_lut dout[4] } "NODE_NAME" } } { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.918 ns ( 46.06 % ) " "Info: Total cell delay = 2.918 ns ( 46.06 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.417 ns ( 53.94 % ) " "Info: Total interconnect delay = 3.417 ns ( 53.94 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.335 ns" { dout[4]~reg0_emulated dout[4]~reg0head_lut dout[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.335 ns" { dout[4]~reg0_emulated {} dout[4]~reg0head_lut {} dout[4] {} } { 0.000ns 0.299ns 3.118ns } { 0.000ns 0.150ns 2.768ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.682 ns" { clk clk~clkctrl dout[4]~reg0_emulated } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "2.682 ns" { clk {} clk~combout {} clk~clkctrl {} dout[4]~reg0_emulated {} } { 0.000ns 0.000ns 0.118ns 1.028ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.335 ns" { dout[4]~reg0_emulated dout[4]~reg0head_lut dout[4] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "6.335 ns" { dout[4]~reg0_emulated {} dout[4]~reg0head_lut {} dout[4] {} } { 0.000ns 0.299ns 3.118ns } { 0.000ns 0.150ns 2.768ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}