prev_cmp_dk74x191.map.qmsg

基于quartus II软件 用verilog语言描述的74ls191

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 09 19:20:23 2008 " "Info: Processing started: Tue Dec 09 19:20:23 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dk74x191 -c dk74x191 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dk74x191 -c dk74x191" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dk74x191.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dk74x191.v" { { "Info" "ISGN_ENTITY_NAME" "1 dk74x191 " "Info: Found entity 1: dk74x191" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dk74x191 " "Info: Elaborating entity \"dk74x191\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Warning" "WOPT_MLS_CREATED_ALOAD_CCT" "" "Warning: Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." { { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[0\]~reg0 dout\[0\]~reg0_emulated dout\[0\]~reg0latch " "Warning (13310): Register \"dout\[0\]~reg0\" is converted into an equivalent circuit using register \"dout\[0\]~reg0_emulated\" and latch \"dout\[0\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[1\]~reg0 dout\[1\]~reg0_emulated dout\[1\]~reg0latch " "Warning (13310): Register \"dout\[1\]~reg0\" is converted into an equivalent circuit using register \"dout\[1\]~reg0_emulated\" and latch \"dout\[1\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[2\]~reg0 dout\[2\]~reg0_emulated dout\[2\]~reg0latch " "Warning (13310): Register \"dout\[2\]~reg0\" is converted into an equivalent circuit using register \"dout\[2\]~reg0_emulated\" and latch \"dout\[2\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[3\]~reg0 dout\[3\]~reg0_emulated dout\[3\]~reg0latch " "Warning (13310): Register \"dout\[3\]~reg0\" is converted into an equivalent circuit using register \"dout\[3\]~reg0_emulated\" and latch \"dout\[3\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[4\]~reg0 dout\[4\]~reg0_emulated dout\[4\]~reg0latch " "Warning (13310): Register \"dout\[4\]~reg0\" is converted into an equivalent circuit using register \"dout\[4\]~reg0_emulated\" and latch \"dout\[4\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[5\]~reg0 dout\[5\]~reg0_emulated dout\[5\]~reg0latch " "Warning (13310): Register \"dout\[5\]~reg0\" is converted into an equivalent circuit using register \"dout\[5\]~reg0_emulated\" and latch \"dout\[5\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[6\]~reg0 dout\[6\]~reg0_emulated dout\[6\]~reg0latch " "Warning (13310): Register \"dout\[6\]~reg0\" is converted into an equivalent circuit using register \"dout\[6\]~reg0_emulated\" and latch \"dout\[6\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0} { "Warning" "WOPT_MLS_CREATED_ALOAD_CCT_SUB" "dout\[7\]~reg0 dout\[7\]~reg0_emulated dout\[7\]~reg0latch " "Warning (13310): Register \"dout\[7\]~reg0\" is converted into an equivalent circuit using register \"dout\[7\]~reg0_emulated\" and latch \"dout\[7\]~reg0latch\"" {  } { { "dk74x191.v" "" { Text "E:/quartus/dk74191/dk74x191.v" 25 -1 0 } }  } 0 13310 "Register \"%1!s!\" is converted into an equivalent circuit using register \"%2!s!\" and latch \"%3!s!\"" 0 0 "" 0 0}  } {  } 0 0 "Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state." 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "57 " "Info: Implemented 57 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "36 " "Info: Implemented 36 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Info: Peak virtual memory: 159 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 09 19:20:28 2008 " "Info: Processing ended: Tue Dec 09 19:20:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}