dk74x191.tmw_info

基于quartus II软件 用verilog语言描述的74ls191

start_full_compilation:s:00:01:13
start_analysis_synthesis:s:00:00:27
start_fitter:s:00:00:30
start_assembler:s:00:00:14
start_timing_analyzer:s:00:00:02
start_generate_netlist:s:00:00:02