dk74x191.tan.rpt

基于quartus II软件 用verilog语言描述的74ls191

; N/A           ; None        ; -2.113 ns ; ld_n   ; dout[2]~reg0_emulated ; clk      ;
; N/A           ; None        ; -2.128 ns ; ld_n   ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -2.278 ns ; ld_n   ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -2.422 ns ; ld_n   ; dout[3]~reg0_emulated ; clk      ;
; N/A           ; None        ; -2.474 ns ; ld_n   ; dout[4]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.306 ns ; din[7] ; dout[7]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -3.314 ns ; din[1] ; dout[1]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -3.321 ns ; s_n    ; dout[2]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.340 ns ; s_n    ; dout[0]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.340 ns ; s_n    ; dout[1]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.340 ns ; s_n    ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.340 ns ; s_n    ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.340 ns ; s_n    ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.458 ns ; din[2] ; dout[2]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -3.566 ns ; s_n    ; dout[3]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.566 ns ; s_n    ; dout[4]~reg0_emulated ; clk      ;
; N/A           ; None        ; -3.654 ns ; din[4] ; dout[4]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -3.667 ns ; din[6] ; dout[6]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -3.708 ns ; din[5] ; dout[5]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -4.082 ns ; din[7] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.347 ns ; din[2] ; dout[2]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.445 ns ; din[3] ; dout[3]~reg0latch     ; ld_n     ;
; N/A           ; None        ; -4.702 ns ; din[5] ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.727 ns ; din[1] ; dout[1]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.787 ns ; din[2] ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.848 ns ; din[2] ; dout[3]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.854 ns ; din[6] ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.928 ns ; din[2] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -4.991 ns ; din[2] ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.029 ns ; din[4] ; dout[4]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.037 ns ; din[2] ; dout[4]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.091 ns ; din[4] ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.103 ns ; din[6] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.159 ns ; din[5] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.222 ns ; din[5] ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.232 ns ; din[4] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.295 ns ; din[4] ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.296 ns ; din[1] ; dout[2]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.421 ns ; din[1] ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.482 ns ; din[1] ; dout[3]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.562 ns ; din[1] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.625 ns ; din[1] ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.671 ns ; din[1] ; dout[4]~reg0_emulated ; clk      ;
; N/A           ; None        ; -5.777 ns ; din[3] ; dout[3]~reg0_emulated ; clk      ;
; N/A           ; None        ; -6.036 ns ; din[3] ; dout[5]~reg0_emulated ; clk      ;
; N/A           ; None        ; -6.177 ns ; din[3] ; dout[7]~reg0_emulated ; clk      ;
; N/A           ; None        ; -6.240 ns ; din[3] ; dout[6]~reg0_emulated ; clk      ;
; N/A           ; None        ; -6.286 ns ; din[3] ; dout[4]~reg0_emulated ; clk      ;
+---------------+-------------+-----------+--------+-----------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Dec 22 15:34:04 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dk74x191 -c dk74x191 --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
    Warning: Node "dout[0]~reg0latch" is a latch
    Warning: Node "dout[1]~reg0latch" is a latch
    Warning: Node "dout[2]~reg0latch" is a latch
    Warning: Node "dout[3]~reg0latch" is a latch
    Warning: Node "dout[4]~reg0latch" is a latch
    Warning: Node "dout[5]~reg0latch" is a latch
    Warning: Node "dout[6]~reg0latch" is a latch
    Warning: Node "dout[7]~reg0latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "ld_n" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Clock "clk" has Internal fmax of 343.52 MHz between source register "dout[2]~reg0_emulated" and destination register "dout[4]~reg0_emulated" (period= 2.911 ns)
    Info: + Longest register to register delay is 2.695 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X42_Y35_N25; Fanout = 1; REG Node = 'dout[2]~reg0_emulated'
        Info: 2: + IC(0.491 ns) + CELL(0.150 ns) = 0.641 ns; Loc. = LCCOMB_X41_Y35_N24; Fanout = 4; COMB Node = 'dout[2]~reg0head_lut'
        Info: 3: + IC(0.271 ns) + CELL(0.414 ns) = 1.326 ns; Loc. = LCCOMB_X41_Y35_N12; Fanout = 2; COMB Node = 'Add1~150'
        Info: 4: + IC(0.000 ns) + CELL(0.159 ns) = 1.485 ns; Loc. = LCCOMB_X41_Y35_N14; Fanout = 2; COMB Node = 'Add1~152'
        Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.895 ns; Loc. = LCCOMB_X41_Y35_N16; Fanout = 1; COMB Node = 'Add1~153'
        Info: 6: + IC(0.441 ns) + CELL(0.275 ns) = 2.611 ns; Loc. = LCCOMB_X40_Y35_N12; Fanout = 1; COMB Node = 'dout[4]~reg0data_lut'
        Info: 7: + IC(0.000 ns) + CELL(0.084 ns) = 2.695 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout[4]~reg0_emulated'
        Info: Total cell delay = 1.492 ns ( 55.36 % )
        Info: Total interconnect delay = 1.203 ns ( 44.64 % )
    Info: - Smallest clock skew is -0.002 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.682 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout[4]~reg0_emulated'
            Info: Total cell delay = 1.536 ns ( 57.27 % )
            Info: Total interconnect delay = 1.146 ns ( 42.73 % )
        Info: - Longest clock path from clock "clk" to source register is 2.684 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(1.030 ns) + CELL(0.537 ns) = 2.684 ns; Loc. = LCFF_X42_Y35_N25; Fanout = 1; REG Node = 'dout[2]~reg0_emulated'
            Info: Total cell delay = 1.536 ns ( 57.23 % )
            Info: Total interconnect delay = 1.148 ns ( 42.77 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "dout[4]~reg0_emulated" (data pin = "din[3]", clock pin = "clk") is 6.516 ns
    Info: + Longest pin to register delay is 9.234 ns
        Info: 1: + IC(0.000 ns) + CELL(0.820 ns) = 0.820 ns; Loc. = PIN_AB15; Fanout = 2; PIN Node = 'din[3]'
        Info: 2: + IC(5.852 ns) + CELL(0.419 ns) = 7.091 ns; Loc. = LCCOMB_X40_Y35_N26; Fanout = 4; COMB Node = 'dout[3]~reg0head_lut'
        Info: 3: + IC(0.448 ns) + CELL(0.485 ns) = 8.024 ns; Loc. = LCCOMB_X41_Y35_N14; Fanout = 2; COMB Node = 'Add1~152'
        Info: 4: + IC(0.000 ns) + CELL(0.410 ns) = 8.434 ns; Loc. = LCCOMB_X41_Y35_N16; Fanout = 1; COMB Node = 'Add1~153'
        Info: 5: + IC(0.441 ns) + CELL(0.275 ns) = 9.150 ns; Loc. = LCCOMB_X40_Y35_N12; Fanout = 1; COMB Node = 'dout[4]~reg0data_lut'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 9.234 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout[4]~reg0_emulated'
        Info: Total cell delay = 2.493 ns ( 27.00 % )
        Info: Total interconnect delay = 6.741 ns ( 73.00 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.682 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout[4]~reg0_emulated'
        Info: Total cell delay = 1.536 ns ( 57.27 % )
        Info: Total interconnect delay = 1.146 ns ( 42.73 % )
Info: tco from clock "clk" to destination pin "dout[4]" through register "dout[4]~reg0_emulated" is 9.267 ns
    Info: + Longest clock path from clock "clk" to source register is 2.682 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 8; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.028 ns) + CELL(0.537 ns) = 2.682 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout[4]~reg0_emulated'
        Info: Total cell delay = 1.536 ns ( 57.27 % )
        Info: Total interconnect delay = 1.146 ns ( 42.73 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 6.335 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y35_N13; Fanout = 1; REG Node = 'dout[4]~reg0_emulated'
        Info: 2: + IC(0.299 ns) + CELL(0.150 ns) = 0.449 ns; Loc. = LCCOMB_X40_Y35_N22; Fanout = 4; COMB Node = 'dout[4]~reg0head_lut'
        Info: 3: + IC(3.118 ns) + CELL(2.768 ns) = 6.335 ns; Loc. = PIN_AC15; Fanout = 0; PIN Node = 'dout[4]'
        Info: Total cell delay = 2.918 ns ( 46.06 % )
        Info: Total interconnect delay = 3.417 ns ( 53.94 % )
Info: Longest tpd from source pin "din[4]" to destination pin "dout[4]" is 12.188 ns
    Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_G16; Fanout = 2; PIN Node = 'din[4]'
    Info: 2: + IC(5.054 ns) + CELL(0.438 ns) = 6.302 ns; Loc. = LCCOMB_X40_Y35_N22; Fanout = 4; COMB Node = 'dout[4]~reg0head_lut'
    Info: 3: + IC(3.118 ns) + CELL(2.768 ns) = 12.188 ns; Loc. = PIN_AC15; Fanout = 0; PIN Node = 'dout[4]'
    Info: Total cell delay = 4.016 ns ( 32.95 % )
    Info: Total interconnect delay = 8.172 ns ( 67.05 % )
Info: th for register "dout[0]~reg0latch" (data pin = "din[0]", clock pin = "ld_n") is 0.071 ns
    Info: + Longest clock path from clock "ld_n" to destination register is 2.603 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 9; CLK Node = 'ld_n'
        Info: 2: + IC(0.113 ns) + CELL(0.000 ns) = 1.112 ns; Loc. = CLKCTRL_G1; Fanout = 16; COMB Node = 'ld_n~clkctrl'
        Info: 3: + IC(1.341 ns) + CELL(0.150 ns) = 2.603 ns; Loc. = LCCOMB_X38_Y35_N0; Fanout = 2; REG Node = 'dout[0]~reg0latch'
        Info: Total cell delay = 1.149 ns ( 44.14 % )
        Info: Total interconnect delay = 1.454 ns ( 55.86 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 2.532 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 2; PIN Node = 'din[0]'
        Info: 2: + IC(1.115 ns) + CELL(0.438 ns) = 2.532 ns; Loc. = LCCOMB_X38_Y35_N0; Fanout = 2; REG Node = 'dout[0]~reg0latch'
        Info: Total cell delay = 1.417 ns ( 55.96 % )
        Info: Total interconnect delay = 1.115 ns ( 44.04 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 10 warnings
    Info: Peak virtual memory: 125 megabytes
    Info: Processing ended: Mon Dec 22 15:34:06 2008
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:01