📄 dk74x191.tan.rpt
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Classic Timing Analyzer report for dk74x191
Mon Dec 22 15:34:05 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.516 ns ; din[3] ; dout[4]~reg0_emulated ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 9.267 ns ; dout[4]~reg0_emulated ; dout[4] ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 12.188 ns ; din[4] ; dout[4] ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.071 ns ; din[0] ; dout[0]~reg0latch ; -- ; ld_n ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 343.52 MHz ( period = 2.911 ns ) ; dout[2]~reg0_emulated ; dout[4]~reg0_emulated ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------------------+-----------------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; ld_n ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 343.52 MHz ( period = 2.911 ns ) ; dout[2]~reg0_emulated ; dout[4]~reg0_emulated ; clk ; clk ; None ; None ; 2.695 ns ;
; N/A ; 349.04 MHz ( period = 2.865 ns ) ; dout[2]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.650 ns ;
; N/A ; 352.24 MHz ( period = 2.839 ns ) ; dout[0]~reg0_emulated ; dout[4]~reg0_emulated ; clk ; clk ; None ; None ; 2.624 ns ;
; N/A ; 355.75 MHz ( period = 2.811 ns ) ; dout[3]~reg0_emulated ; dout[4]~reg0_emulated ; clk ; clk ; None ; None ; 2.597 ns ;
; N/A ; 356.89 MHz ( period = 2.802 ns ) ; dout[2]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.587 ns ;
; N/A ; 358.04 MHz ( period = 2.793 ns ) ; dout[0]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.579 ns ;
; N/A ; 361.66 MHz ( period = 2.765 ns ) ; dout[3]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.552 ns ;
; N/A ; 361.79 MHz ( period = 2.764 ns ) ; dout[1]~reg0_emulated ; dout[4]~reg0_emulated ; clk ; clk ; None ; None ; 2.549 ns ;
; N/A ; 366.30 MHz ( period = 2.730 ns ) ; dout[0]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.516 ns ;
; N/A ; 367.38 MHz ( period = 2.722 ns ) ; dout[2]~reg0_emulated ; dout[3]~reg0_emulated ; clk ; clk ; None ; None ; 2.506 ns ;
; N/A ; 367.92 MHz ( period = 2.718 ns ) ; dout[1]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.504 ns ;
; N/A ; 368.05 MHz ( period = 2.717 ns ) ; dout[5]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.503 ns ;
; N/A ; 370.10 MHz ( period = 2.702 ns ) ; dout[3]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.489 ns ;
; N/A ; 375.80 MHz ( period = 2.661 ns ) ; dout[2]~reg0_emulated ; dout[5]~reg0_emulated ; clk ; clk ; None ; None ; 2.446 ns ;
; N/A ; 376.65 MHz ( period = 2.655 ns ) ; dout[1]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.441 ns ;
; N/A ; 376.79 MHz ( period = 2.654 ns ) ; dout[5]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.440 ns ;
; N/A ; 377.36 MHz ( period = 2.650 ns ) ; dout[0]~reg0_emulated ; dout[3]~reg0_emulated ; clk ; clk ; None ; None ; 2.435 ns ;
; N/A ; 384.02 MHz ( period = 2.604 ns ) ; dout[4]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.391 ns ;
; N/A ; 385.21 MHz ( period = 2.596 ns ) ; dout[6]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.382 ns ;
; N/A ; 386.25 MHz ( period = 2.589 ns ) ; dout[0]~reg0_emulated ; dout[5]~reg0_emulated ; clk ; clk ; None ; None ; 2.375 ns ;
; N/A ; 388.35 MHz ( period = 2.575 ns ) ; dout[1]~reg0_emulated ; dout[3]~reg0_emulated ; clk ; clk ; None ; None ; 2.360 ns ;
; N/A ; 390.47 MHz ( period = 2.561 ns ) ; dout[3]~reg0_emulated ; dout[5]~reg0_emulated ; clk ; clk ; None ; None ; 2.348 ns ;
; N/A ; 393.55 MHz ( period = 2.541 ns ) ; dout[4]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 2.328 ns ;
; N/A ; 397.77 MHz ( period = 2.514 ns ) ; dout[1]~reg0_emulated ; dout[5]~reg0_emulated ; clk ; clk ; None ; None ; 2.300 ns ;
; N/A ; 405.84 MHz ( period = 2.464 ns ) ; dout[0]~reg0_emulated ; dout[2]~reg0_emulated ; clk ; clk ; None ; None ; 2.251 ns ;
; N/A ; 416.67 MHz ( period = 2.400 ns ) ; dout[4]~reg0_emulated ; dout[5]~reg0_emulated ; clk ; clk ; None ; None ; 2.187 ns ;
; N/A ; 418.59 MHz ( period = 2.389 ns ) ; dout[1]~reg0_emulated ; dout[2]~reg0_emulated ; clk ; clk ; None ; None ; 2.176 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[6]~reg0_emulated ; dout[6]~reg0_emulated ; clk ; clk ; None ; None ; 2.133 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[4]~reg0_emulated ; dout[4]~reg0_emulated ; clk ; clk ; None ; None ; 2.124 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[3]~reg0_emulated ; dout[3]~reg0_emulated ; clk ; clk ; None ; None ; 2.088 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[2]~reg0_emulated ; dout[2]~reg0_emulated ; clk ; clk ; None ; None ; 2.007 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[0]~reg0_emulated ; dout[1]~reg0_emulated ; clk ; clk ; None ; None ; 1.997 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[5]~reg0_emulated ; dout[5]~reg0_emulated ; clk ; clk ; None ; None ; 1.983 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[0]~reg0_emulated ; dout[0]~reg0_emulated ; clk ; clk ; None ; None ; 1.815 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[7]~reg0_emulated ; dout[7]~reg0_emulated ; clk ; clk ; None ; None ; 1.721 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; dout[1]~reg0_emulated ; dout[1]~reg0_emulated ; clk ; clk ; None ; None ; 1.606 ns ;
+-------+------------------------------------------------+-----------------------+-----------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-------------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+--------+-----------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+--------+-----------------------+----------+
; N/A ; None ; 6.516 ns ; din[3] ; dout[4]~reg0_emulated ; clk ;
; N/A ; None ; 6.470 ns ; din[3] ; dout[6]~reg0_emulated ; clk ;
; N/A ; None ; 6.407 ns ; din[3] ; dout[7]~reg0_emulated ; clk ;
; N/A ; None ; 6.266 ns ; din[3] ; dout[5]~reg0_emulated ; clk ;
; N/A ; None ; 6.007 ns ; din[3] ; dout[3]~reg0_emulated ; clk ;
; N/A ; None ; 5.901 ns ; din[1] ; dout[4]~reg0_emulated ; clk ;
; N/A ; None ; 5.855 ns ; din[1] ; dout[6]~reg0_emulated ; clk ;
; N/A ; None ; 5.792 ns ; din[1] ; dout[7]~reg0_emulated ; clk ;
; N/A ; None ; 5.712 ns ; din[1] ; dout[3]~reg0_emulated ; clk ;
; N/A ; None ; 5.651 ns ; din[1] ; dout[5]~reg0_emulated ; clk ;
; N/A ; None ; 5.526 ns ; din[1] ; dout[2]~reg0_emulated ; clk ;
; N/A ; None ; 5.525 ns ; din[4] ; dout[6]~reg0_emulated ; clk ;
; N/A ; None ; 5.462 ns ; din[4] ; dout[7]~reg0_emulated ; clk ;
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