dk74x191.v.bak

来自「基于quartus II软件 用verilog语言描述的74ls191」· BAK 代码 · 共 60 行

module dk74x191(clk,s_n,ld_n,u_d,din,dout,c);

input clk, s_n, ld_n,u_d;
input [7:0]din;
output [7:0]dout;
output c;
reg [7:0]dout;
reg c;

wire s,ld;

//assign s=!s_n;
assign ld=!ld_n;

always@(posedge clk or posedge s_n or posedge ld)
begin
	if(ld)
		begin
			dout=8'b00000000;
		end
	else if(s_n)
			begin
				dout=dout;
			end
		 else if(u_d) 
				begin 
					dout=dout-1'b1;
				end
			  else 
				begin
					dout=dout+1'b1;
				end
end
always@(dout or u_d)
begin
	if(u_d)
		begin
			if(dout==8'b00000000)
				begin
					c=1'b1;
				end
			else
				begin
					c=1'b0;
				end
		end
	else
		begin
			if(dout==8'b11111111)
				begin
					c=1'b1;
				end
			 else
				begin
					c=1'b0;
				end
		end
end
endmodule