dk74x191.tan.summary

基于quartus II软件 用verilog语言描述的74ls191

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.516 ns
From           : din[3]
To             : dout[4]~reg0_emulated
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.267 ns
From           : dout[4]~reg0_emulated
To             : dout[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 12.188 ns
From           : din[4]
To             : dout[4]
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 0.071 ns
From           : din[0]
To             : dout[0]~reg0latch
From Clock     : --
To Clock       : ld_n
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 343.52 MHz ( period = 2.911 ns )
From           : dout[2]~reg0_emulated
To             : dout[4]~reg0_emulated
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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