dk74x161.tan.rpt

给予quartus II 软件 verilog 描述的 74ls161 包含仿真波形

+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 8.185 ns   ; dout[2]~reg0 ; dout[2] ; clk        ;
; N/A   ; None         ; 7.939 ns   ; dout[0]~reg0 ; c       ; clk        ;
; N/A   ; None         ; 7.898 ns   ; dout[1]~reg0 ; c       ; clk        ;
; N/A   ; None         ; 7.791 ns   ; dout[2]~reg0 ; c       ; clk        ;
; N/A   ; None         ; 7.649 ns   ; dout[3]~reg0 ; c       ; clk        ;
; N/A   ; None         ; 6.623 ns   ; dout[0]~reg0 ; dout[0] ; clk        ;
; N/A   ; None         ; 6.622 ns   ; dout[3]~reg0 ; dout[3] ; clk        ;
; N/A   ; None         ; 6.395 ns   ; dout[1]~reg0 ; dout[1] ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+---------------------------------------------------------+
; tpd                                                     ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A   ; None              ; 7.404 ns        ; rd_n ; c  ;
; N/A   ; None              ; 5.909 ns        ; et   ; c  ;
+-------+-------------------+-----------------+------+----+


+----------------------------------------------------------------------------+
; th                                                                         ;
+---------------+-------------+-----------+--------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To           ; To Clock ;
+---------------+-------------+-----------+--------+--------------+----------+
; N/A           ; None        ; 0.293 ns  ; ep     ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; 0.150 ns  ; et     ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -0.090 ns ; ep     ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.161 ns ; ep     ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.232 ns ; ep     ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -0.233 ns ; et     ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -0.304 ns ; et     ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -0.375 ns ; et     ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.114 ns ; din[3] ; dout[3]~reg0 ; clk      ;
; N/A           ; None        ; -3.773 ns ; din[1] ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -3.823 ns ; din[2] ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -3.860 ns ; din[0] ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -4.077 ns ; ld_n   ; dout[0]~reg0 ; clk      ;
; N/A           ; None        ; -4.077 ns ; ld_n   ; dout[1]~reg0 ; clk      ;
; N/A           ; None        ; -4.077 ns ; ld_n   ; dout[2]~reg0 ; clk      ;
; N/A           ; None        ; -4.077 ns ; ld_n   ; dout[3]~reg0 ; clk      ;
+---------------+-------------+-----------+--------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Dec 08 21:35:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off dk74x161 -c dk74x161 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "dout[0]~reg0" and destination register "dout[3]~reg0"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.388 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y34_N21; Fanout = 4; REG Node = 'dout[0]~reg0'
            Info: 2: + IC(0.338 ns) + CELL(0.414 ns) = 0.752 ns; Loc. = LCCOMB_X33_Y34_N20; Fanout = 2; COMB Node = 'dout[0]~57'
            Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.823 ns; Loc. = LCCOMB_X33_Y34_N22; Fanout = 2; COMB Node = 'dout[1]~59'
            Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 0.894 ns; Loc. = LCCOMB_X33_Y34_N24; Fanout = 1; COMB Node = 'dout[2]~61'
            Info: 5: + IC(0.000 ns) + CELL(0.410 ns) = 1.304 ns; Loc. = LCCOMB_X33_Y34_N26; Fanout = 1; COMB Node = 'dout[3]~62'
            Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 1.388 ns; Loc. = LCFF_X33_Y34_N27; Fanout = 3; REG Node = 'dout[3]~reg0'
            Info: Total cell delay = 1.050 ns ( 75.65 % )
            Info: Total interconnect delay = 0.338 ns ( 24.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.668 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X33_Y34_N27; Fanout = 3; REG Node = 'dout[3]~reg0'
                Info: Total cell delay = 1.536 ns ( 57.57 % )
                Info: Total interconnect delay = 1.132 ns ( 42.43 % )
            Info: - Longest clock path from clock "clk" to source register is 2.668 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X33_Y34_N21; Fanout = 4; REG Node = 'dout[0]~reg0'
                Info: Total cell delay = 1.536 ns ( 57.57 % )
                Info: Total interconnect delay = 1.132 ns ( 42.43 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "dout[0]~reg0" (data pin = "ld_n", clock pin = "clk") is 4.307 ns
    Info: + Longest pin to register delay is 7.011 ns
        Info: 1: + IC(0.000 ns) + CELL(0.842 ns) = 0.842 ns; Loc. = PIN_E5; Fanout = 4; PIN Node = 'ld_n'
        Info: 2: + IC(5.510 ns) + CELL(0.659 ns) = 7.011 ns; Loc. = LCFF_X33_Y34_N21; Fanout = 4; REG Node = 'dout[0]~reg0'
        Info: Total cell delay = 1.501 ns ( 21.41 % )
        Info: Total interconnect delay = 5.510 ns ( 78.59 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.668 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X33_Y34_N21; Fanout = 4; REG Node = 'dout[0]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.57 % )
        Info: Total interconnect delay = 1.132 ns ( 42.43 % )
Info: tco from clock "clk" to destination pin "dout[2]" through register "dout[2]~reg0" is 8.185 ns
    Info: + Longest clock path from clock "clk" to source register is 2.668 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X33_Y34_N25; Fanout = 4; REG Node = 'dout[2]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.57 % )
        Info: Total interconnect delay = 1.132 ns ( 42.43 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.267 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X33_Y34_N25; Fanout = 4; REG Node = 'dout[2]~reg0'
        Info: 2: + IC(2.605 ns) + CELL(2.662 ns) = 5.267 ns; Loc. = PIN_B2; Fanout = 0; PIN Node = 'dout[2]'
        Info: Total cell delay = 2.662 ns ( 50.54 % )
        Info: Total interconnect delay = 2.605 ns ( 49.46 % )
Info: Longest tpd from source pin "rd_n" to destination pin "c" is 7.404 ns
    Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 2; PIN Node = 'rd_n'
    Info: 2: + IC(2.146 ns) + CELL(0.393 ns) = 3.538 ns; Loc. = LCCOMB_X33_Y34_N18; Fanout = 1; COMB Node = 'c~43'
    Info: 3: + IC(1.098 ns) + CELL(2.768 ns) = 7.404 ns; Loc. = PIN_F12; Fanout = 0; PIN Node = 'c'
    Info: Total cell delay = 4.160 ns ( 56.19 % )
    Info: Total interconnect delay = 3.244 ns ( 43.81 % )
Info: th for register "dout[0]~reg0" (data pin = "ep", clock pin = "clk") is 0.293 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.668 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(1.014 ns) + CELL(0.537 ns) = 2.668 ns; Loc. = LCFF_X33_Y34_N21; Fanout = 4; REG Node = 'dout[0]~reg0'
        Info: Total cell delay = 1.536 ns ( 57.57 % )
        Info: Total interconnect delay = 1.132 ns ( 42.43 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.641 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'ep'
        Info: 2: + IC(0.762 ns) + CELL(0.150 ns) = 1.891 ns; Loc. = LCCOMB_X33_Y34_N4; Fanout = 2; COMB Node = 'Decoder0~15'
        Info: 3: + IC(0.246 ns) + CELL(0.420 ns) = 2.557 ns; Loc. = LCCOMB_X33_Y34_N20; Fanout = 1; COMB Node = 'dout[0]~56'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 2.641 ns; Loc. = LCFF_X33_Y34_N21; Fanout = 4; REG Node = 'dout[0]~reg0'
        Info: Total cell delay = 1.633 ns ( 61.83 % )
        Info: Total interconnect delay = 1.008 ns ( 38.17 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 126 megabytes
    Info: Processing ended: Mon Dec 08 21:35:31 2008
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:01