color.tan.rpt

vga在vhdl下的 图像控制 一种方法

; N/A           ; None             ; 18.028 ns      ; LL[8]  ; VS ; CLK        ;
; N/A           ; None             ; 18.145 ns      ; LL[5]  ; VS ; CLK        ;
; N/A           ; None             ; 18.238 ns      ; LL[6]  ; R  ; CLK        ;
; N/A           ; None             ; 18.244 ns      ; LL[6]  ; G  ; CLK        ;
; N/A           ; None             ; 18.489 ns      ; LL[7]  ; R  ; CLK        ;
; N/A           ; None             ; 18.495 ns      ; LL[7]  ; G  ; CLK        ;
; N/A           ; None             ; 18.537 ns      ; LL[8]  ; R  ; CLK        ;
; N/A           ; None             ; 18.543 ns      ; LL[8]  ; G  ; CLK        ;
; N/A           ; None             ; 18.562 ns      ; LL[6]  ; B  ; CLK        ;
; N/A           ; None             ; 18.654 ns      ; LL[5]  ; R  ; CLK        ;
; N/A           ; None             ; 18.660 ns      ; LL[5]  ; G  ; CLK        ;
; N/A           ; None             ; 18.813 ns      ; LL[7]  ; B  ; CLK        ;
; N/A           ; None             ; 18.861 ns      ; LL[8]  ; B  ; CLK        ;
; N/A           ; None             ; 18.978 ns      ; LL[5]  ; B  ; CLK        ;
; N/A           ; None             ; 20.133 ns      ; LL[4]  ; G  ; CLK        ;
; N/A           ; None             ; 21.143 ns      ; LL[4]  ; R  ; CLK        ;
; N/A           ; None             ; 21.439 ns      ; LL[3]  ; R  ; CLK        ;
; N/A           ; None             ; 21.739 ns      ; LL[4]  ; B  ; CLK        ;
; N/A           ; None             ; 23.038 ns      ; LL[3]  ; B  ; CLK        ;
; N/A           ; None             ; 23.173 ns      ; LL[2]  ; B  ; CLK        ;
+---------------+------------------+----------------+--------+----+------------+


+-----------------------------------------------------------------+
; Minimum tpd                                                     ;
+---------------+-------------------+-----------------+------+----+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+---------------+-------------------+-----------------+------+----+
; N/A           ; None              ; 11.069 ns       ; MD   ; R  ;
; N/A           ; None              ; 11.075 ns       ; MD   ; G  ;
; N/A           ; None              ; 11.396 ns       ; MD   ; B  ;
+---------------+-------------------+-----------------+------+----+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue May 10 15:13:26 2005
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off COLOR -c COLOR --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK is an undefined clock
    Info: Assuming node MD is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock FS[3] as buffer
    Info: Detected ripple clock CC[4] as buffer
Info: Clock CLK Internal fmax is restricted to 275.03 MHz between source register LL[0] and destination register LL[7]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 3.368 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X10_Y10_N9; Fanout = 8; REG Node = 'LL[0]'
            Info: 2: + IC(0.524 ns) + CELL(0.564 ns) = 1.088 ns; Loc. = LC_X10_Y10_N0; Fanout = 2; COMB Node = 'add~39COUT0'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.166 ns; Loc. = LC_X10_Y10_N1; Fanout = 2; COMB Node = 'add~40COUT0'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.244 ns; Loc. = LC_X10_Y10_N2; Fanout = 2; COMB Node = 'add~41COUT0'
            Info: 5: + IC(0.000 ns) + CELL(0.078 ns) = 1.322 ns; Loc. = LC_X10_Y10_N3; Fanout = 2; COMB Node = 'add~42COUT0'
            Info: 6: + IC(0.000 ns) + CELL(0.178 ns) = 1.500 ns; Loc. = LC_X10_Y10_N4; Fanout = 4; COMB Node = 'add~43COUT'
            Info: 7: + IC(0.000 ns) + CELL(0.621 ns) = 2.121 ns; Loc. = LC_X10_Y10_N7; Fanout = 1; COMB Node = 'add~46'
            Info: 8: + IC(0.769 ns) + CELL(0.478 ns) = 3.368 ns; Loc. = LC_X9_Y10_N1; Fanout = 10; REG Node = 'LL[7]'
            Info: Total cell delay = 2.075 ns ( 61.61 % )
            Info: Total interconnect delay = 1.293 ns ( 38.39 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock CLK to destination register is 12.371 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.565 ns) + CELL(0.935 ns) = 2.969 ns; Loc. = LC_X8_Y10_N5; Fanout = 8; REG Node = 'FS[3]'
                Info: 3: + IC(3.645 ns) + CELL(0.935 ns) = 7.549 ns; Loc. = LC_X8_Y11_N7; Fanout = 15; REG Node = 'CC[4]'
                Info: 4: + IC(4.111 ns) + CELL(0.711 ns) = 12.371 ns; Loc. = LC_X9_Y10_N1; Fanout = 10; REG Node = 'LL[7]'
                Info: Total cell delay = 4.050 ns ( 32.74 % )
                Info: Total interconnect delay = 8.321 ns ( 67.26 % )
            Info: - Longest clock path from clock CLK to source register is 12.371 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK'
                Info: 2: + IC(0.565 ns) + CELL(0.935 ns) = 2.969 ns; Loc. = LC_X8_Y10_N5; Fanout = 8; REG Node = 'FS[3]'
                Info: 3: + IC(3.645 ns) + CELL(0.935 ns) = 7.549 ns; Loc. = LC_X8_Y11_N7; Fanout = 15; REG Node = 'CC[4]'
                Info: 4: + IC(4.111 ns) + CELL(0.711 ns) = 12.371 ns; Loc. = LC_X10_Y10_N9; Fanout = 8; REG Node = 'LL[0]'
                Info: Total cell delay = 4.050 ns ( 32.74 % )
                Info: Total interconnect delay = 8.321 ns ( 67.26 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: Clock MD Internal fmax is restricted to 275.03 MHz between source register MMD[0] and destination register MMD[0]
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.207 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y12_N3; Fanout = 5; REG Node = 'MMD[0]'
            Info: 2: + IC(0.600 ns) + CELL(0.607 ns) = 1.207 ns; Loc. = LC_X9_Y12_N3; Fanout = 5; REG Node = 'MMD[0]'
            Info: Total cell delay = 0.607 ns ( 50.29 % )
            Info: Total interconnect delay = 0.600 ns ( 49.71 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock MD to destination register is 6.922 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 5; CLK Node = 'MD'
                Info: 2: + IC(4.742 ns) + CELL(0.711 ns) = 6.922 ns; Loc. = LC_X9_Y12_N3; Fanout = 5; REG Node = 'MMD[0]'
                Info: Total cell delay = 2.180 ns ( 31.49 % )
                Info: Total interconnect delay = 4.742 ns ( 68.51 % )
            Info: - Longest clock path from clock MD to source register is 6.922 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 5; CLK Node = 'MD'
                Info: 2: + IC(4.742 ns) + CELL(0.711 ns) = 6.922 ns; Loc. = LC_X9_Y12_N3; Fanout = 5; REG Node = 'MMD[0]'
                Info: Total cell delay = 2.180 ns ( 31.49 % )
                Info: Total interconnect delay = 4.742 ns ( 68.51 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock CLK to destination pin B through register LL[3] is 24.915 ns
    Info: + Longest clock path from clock CLK to source register is 12.371 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.565 ns) + CELL(0.935 ns) = 2.969 ns; Loc. = LC_X8_Y10_N5; Fanout = 8; REG Node = 'FS[3]'
        Info: 3: + IC(3.645 ns) + CELL(0.935 ns) = 7.549 ns; Loc. = LC_X8_Y11_N7; Fanout = 15; REG Node = 'CC[4]'
        Info: 4: + IC(4.111 ns) + CELL(0.711 ns) = 12.371 ns; Loc. = LC_X9_Y10_N0; Fanout = 8; REG Node = 'LL[3]'
        Info: Total cell delay = 4.050 ns ( 32.74 % )
        Info: Total interconnect delay = 8.321 ns ( 67.26 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 12.320 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y10_N0; Fanout = 8; REG Node = 'LL[3]'
        Info: 2: + IC(2.006 ns) + CELL(0.114 ns) = 2.120 ns; Loc. = LC_X9_Y10_N7; Fanout = 1; COMB Node = 'GRBY[1]~783'
        Info: 3: + IC(1.933 ns) + CELL(0.114 ns) = 4.167 ns; Loc. = LC_X9_Y10_N3; Fanout = 1; COMB Node = 'GRBY[1]~784'
        Info: 4: + IC(1.254 ns) + CELL(0.292 ns) = 5.713 ns; Loc. = LC_X9_Y12_N7; Fanout = 1; COMB Node = 'GRBY[1]~824'
        Info: 5: + IC(1.107 ns) + CELL(0.292 ns) = 7.112 ns; Loc. = LC_X9_Y12_N6; Fanout = 1; COMB Node = 'GRBP[1]~728'
        Info: 6: + IC(1.093 ns) + CELL(0.442 ns) = 8.647 ns; Loc. = LC_X9_Y13_N2; Fanout = 1; COMB Node = 'GRB[1]'
        Info: 7: + IC(1.565 ns) + CELL(2.108 ns) = 12.320 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'B'
        Info: Total cell delay = 3.362 ns ( 27.29 % )
        Info: Total interconnect delay = 8.958 ns ( 72.71 % )
Info: Longest tpd from source pin MD to destination pin B is 11.396 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 5; CLK Node = 'MD'
    Info: 2: + IC(5.664 ns) + CELL(0.590 ns) = 7.723 ns; Loc. = LC_X9_Y13_N2; Fanout = 1; COMB Node = 'GRB[1]'
    Info: 3: + IC(1.565 ns) + CELL(2.108 ns) = 11.396 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'B'
    Info: Total cell delay = 4.167 ns ( 36.57 % )
    Info: Total interconnect delay = 7.229 ns ( 63.43 % )
Info: Minimum tco from clock CLK to destination pin HS through register CC[3] is 12.185 ns
    Info: + Shortest clock path from clock CLK to source register is 7.325 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_92; Fanout = 4; CLK Node = 'CLK'
        Info: 2: + IC(0.565 ns) + CELL(0.935 ns) = 2.969 ns; Loc. = LC_X8_Y10_N5; Fanout = 8; REG Node = 'FS[3]'
        Info: 3: + IC(3.645 ns) + CELL(0.711 ns) = 7.325 ns; Loc. = LC_X8_Y11_N9; Fanout = 8; REG Node = 'CC[3]'
        Info: Total cell delay = 3.115 ns ( 42.53 % )
        Info: Total interconnect delay = 4.210 ns ( 57.47 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Shortest register to pin delay is 4.636 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y11_N9; Fanout = 8; REG Node = 'CC[3]'
        Info: 2: + IC(0.555 ns) + CELL(0.292 ns) = 0.847 ns; Loc. = LC_X8_Y11_N5; Fanout = 5; COMB Node = 'LessThan~581'
        Info: 3: + IC(1.681 ns) + CELL(2.108 ns) = 4.636 ns; Loc. = PIN_139; Fanout = 0; PIN Node = 'HS'
        Info: Total cell delay = 2.400 ns ( 51.77 % )
        Info: Total interconnect delay = 2.236 ns ( 48.23 % )
Info: Shortest tpd from source pin MD to destination pin R is 11.069 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_1; Fanout = 5; CLK Node = 'MD'
    Info: 2: + IC(5.664 ns) + CELL(0.590 ns) = 7.723 ns; Loc. = LC_X9_Y13_N4; Fanout = 1; COMB Node = 'GRB[2]'
    Info: 3: + IC(1.238 ns) + CELL(2.108 ns) = 11.069 ns; Loc. = PIN_131; Fanout = 0; PIN Node = 'R'
    Info: Total cell delay = 4.167 ns ( 37.65 % )
    Info: Total interconnect delay = 6.902 ns ( 62.35 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue May 10 15:13:27 2005
    Info: Elapsed time: 00:00:00