📄 color.fit.rpt
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; Local interconnects ; 71 / 11,506 ( < 1 % ) ;
; M4K buffers ; 0 / 468 ( 0 % ) ;
; R4s ; 29 / 7,520 ( < 1 % ) ;
+----------------------------+-----------------------+
+--------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-----------------------------+
; Number of Logic Elements (Average = 7.13) ; Number of LABs (Total = 8) ;
+--------------------------------------------+-----------------------------+
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 4 ;
+--------------------------------------------+-----------------------------+
+------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-----------------------------+
; LAB-wide Signals (Average = 0.75) ; Number of LABs (Total = 8) ;
+------------------------------------+-----------------------------+
; 1 Clock ; 6 ;
+------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+-----------------------------+
; Number of Signals Sourced (Average = 7.63) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 1 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 2 ;
; 11 ; 1 ;
; 12 ; 0 ;
; 13 ; 1 ;
+---------------------------------------------+-----------------------------+
+-------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-----------------------------+
; Number of Signals Sourced Out (Average = 5.13) ; Number of LABs (Total = 8) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 1 ;
+-------------------------------------------------+-----------------------------+
+---------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+-----------------------------+
; Number of Distinct Inputs (Average = 7.00) ; Number of LABs (Total = 8) ;
+---------------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 2 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 1 ;
; 11 ; 2 ;
+---------------------------------------------+-----------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
Info: Processing started: Tue May 10 15:13:16 2005
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off COLOR -c COLOR
Info: Selected device EP1C3T144C8 for design COLOR
Info: Fitter is performing a Standard Fit compilation -- maximum Fitter effort will be used to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EP1C6T144C8 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal CLK to use Global clock in PIN 92
Info: Automatically promoted some destinations of signal CC[4] to use Global clock
Info: Destination LessThan~581 may be non-global or may not use global clock
Info: Destination GRBX[2]~492 may be non-global or may not use global clock
Info: Destination GRBX~30 may be non-global or may not use global clock
Info: Destination GRBX[1]~486 may be non-global or may not use global clock
Info: Destination GRBX[1]~487 may be non-global or may not use global clock
Info: Destination add~38 may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal FS[3] to use Global clock
Info: Destination FS[3] may be non-global or may not use global clock
Info: Destination FS[0] may be non-global or may not use global clock
Info: Destination FS[2] may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal MD to use Global clock
Info: Destination GRB[2] may be non-global or may not use global clock
Info: Destination GRB[3] may be non-global or may not use global clock
Info: Destination GRB[1] may be non-global or may not use global clock
Info: Pin MD drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP scan-chain inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 0 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 3.248 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y10; Fanout = 4; REG Node = 'LL[1]'
Info: 2: + IC(0.617 ns) + CELL(0.575 ns) = 1.192 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'add~40COUT1'
Info: 3: + IC(0.000 ns) + CELL(0.080 ns) = 1.272 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'add~41COUT1'
Info: 4: + IC(0.000 ns) + CELL(0.080 ns) = 1.352 ns; Loc. = LAB_X10_Y10; Fanout = 2; COMB Node = 'add~42COUT1'
Info: 5: + IC(0.000 ns) + CELL(0.258 ns) = 1.610 ns; Loc. = LAB_X10_Y10; Fanout = 4; COMB Node = 'add~43COUT'
Info: 6: + IC(0.000 ns) + CELL(0.679 ns) = 2.289 ns; Loc. = LAB_X10_Y10; Fanout = 1; COMB Node = 'add~45'
Info: 7: + IC(0.221 ns) + CELL(0.738 ns) = 3.248 ns; Loc. = LAB_X9_Y10; Fanout = 10; REG Node = 'LL[6]'
Info: Total cell delay = 2.410 ns ( 74.20 % )
Info: Total interconnect delay = 0.838 ns ( 25.80 % )
Info: Estimated interconnect usage is 1% of the available device resources
Info: Fitter placement operations ending: elapsed time = 0 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Tue May 10 15:13:23 2005
Info: Elapsed time: 00:00:06
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