color.qsf

vga在vhdl下的 图像控制 一种方法

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		COLOR_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "08:14:13  JANUARY 29, 2005"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name VHDL_FILE color.vhd

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_1 -to MD
set_location_assignment PIN_140 -to VS
set_location_assignment PIN_139 -to HS
set_location_assignment PIN_131 -to R
set_location_assignment PIN_132 -to G
set_location_assignment PIN_134 -to B
set_location_assignment PIN_92 -to CLK

# Timing Assignments
# ==================
set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS OFF

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL SYNPLIFY
set_global_assignment -name FAMILY Cyclone
set_global_assignment -name TOP_LEVEL_ENTITY COLOR

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE EP1C3T144C8
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX7000B_VCCIO_IOBANK2 3.3V
set_global_assignment -name MAX7000B_VCCIO_IOBANK1 3.3V

# Timing Analysis Assignments
# ===========================
set_global_assignment -name EXCLUDE_TPD_PATHS_LESS_THAN 0.0NS

# Assembler Assignments
# =====================
set_global_assignment -name AUTO_RESTART_CONFIGURATION OFF

# Simulator Assignments
# =====================
set_global_assignment -name START_TIME "0 ns"
set_global_assignment -name GLITCH_INTERVAL 0.0ns
set_global_assignment -name END_TIME 0.0ns

# LogicLock Region Assignments
# ============================
set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF

# ---------------------------------------------
# start EDA_TOOL_SETTINGS(eda_design_synthesis)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis

# end EDA_TOOL_SETTINGS(eda_design_synthesis)
# -------------------------------------------

# -------------------
# start ENTITY(color)

	# Analysis & Synthesis Assignments
	# ================================
	set_global_assignment -name AUTO_LCELL_INSERTION ON -entity color

# end ENTITY(color)
# -----------------