color.map.rpt

vga在vhdl下的 图像控制 一种方法

; 2:1                ; 2 bits    ; 2 LEs         ; 2 LEs                ; 0 LEs                  ; No         ; |COLOR|GRBX~6              ;
; 2:1                ; 2 bits    ; 2 LEs         ; 2 LEs                ; 0 LEs                  ; No         ; |COLOR|GRBX[2]             ;
; 2:1                ; 3 bits    ; 3 LEs         ; 3 LEs                ; 0 LEs                  ; No         ; |COLOR|GRBY~6              ;
; 2:1                ; 2 bits    ; 2 LEs         ; 2 LEs                ; 0 LEs                  ; No         ; |COLOR|GRBY[2]             ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |COLOR|GRBP[2]             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+----------------------------------------------------------------+
; WYSIWYG Cells                                                  ;
+--------------------------------------------------------+-------+
; Statistic                                              ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells                                ; 14    ;
; Number of synthesis-generated cells                    ; 47    ;
; Number of WYSIWYG LUTs                                 ; 14    ;
; Number of synthesis-generated LUTs                     ; 41    ;
; Number of WYSIWYG registers                            ; 0     ;
; Number of synthesis-generated registers                ; 20    ;
; Number of cells with combinational logic only          ; 41    ;
; Number of cells with registers only                    ; 6     ;
; Number of cells with combinational logic and registers ; 14    ;
+--------------------------------------------------------+-------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 1     ;
; Number of registers using Output Enable      ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------+
; Hierarchy ;
+-----------+
COLOR


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+
; |COLOR                     ; 61 (61)     ; 20           ; 0           ; 7    ; 0            ; 41 (41)      ; 6 (6)             ; 14 (14)          ; 14 (14)         ; |COLOR              ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+---------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/EDA_VHDL_Expt3/Chapter13_A/EP1C3_13_3_VGA/COLOR.map.eqn.


+----------------------------------------+
; Analysis & Synthesis Source Files Read ;
+-----------+----------------------------+
; File Name ; Used in Netlist            ;
+-----------+----------------------------+
; color.vhd ; yes                        ;
+-----------+----------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource                          ; Usage   ;
+-----------------------------------+---------+
; Logic cells                       ; 61      ;
; Total combinational functions     ; 55      ;
; Total 4-input functions           ; 28      ;
; Total 3-input functions           ; 4       ;
; Total 2-input functions           ; 9       ;
; Total 1-input functions           ; 14      ;
; Total 0-input functions           ; 0       ;
; Combinational cells for routing   ; 0       ;
; Total registers                   ; 20      ;
; Total logic cells in carry chains ; 14      ;
; I/O pins                          ; 7       ;
; Maximum fan-out node              ; CC[4]   ;
; Maximum fan-out                   ; 15      ;
; Total fan-out                     ; 200     ;
; Average fan-out                   ; 2.94    ;
+-----------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Tue May 10 15:13:10 2005
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off COLOR -c COLOR
Info: Found 2 design units, including 1 entities, in source file color.vhd
    Info: Found design unit 1: COLOR-behav
    Info: Found entity 1: COLOR
Warning: VHDL Process Statement warning at color.vhd(31): signal grbx is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at color.vhd(32): signal grby is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at color.vhd(33): signal grbx is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at color.vhd(33): signal grby is in statement, but is not in sensitivity list
Info: Implemented 68 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 5 output pins
    Info: Implemented 61 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Tue May 10 15:13:15 2005
    Info: Elapsed time: 00:00:05