steady_switch.tan.qmsg

消除抖动的双稳定开关

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register state.s3 state.s1 500.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 500.0 MHz between source register \"state.s3\" and destination register \"state.s1\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.607 ns + Longest register register " "Info: + Longest register to register delay is 0.607 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s3 1 REG LCFF_X39_Y22_N9 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y22_N9; Fanout = 3; REG Node = 'state.s3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.s3 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.227 ns) + CELL(0.225 ns) 0.452 ns Selector1~7 2 COMB LCCOMB_X39_Y22_N22 1 " "Info: 2: + IC(0.227 ns) + CELL(0.225 ns) = 0.452 ns; Loc. = LCCOMB_X39_Y22_N22; Fanout = 1; COMB Node = 'Selector1~7'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.452 ns" { state.s3 Selector1~7 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.607 ns state.s1 3 REG LCFF_X39_Y22_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.607 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Selector1~7 state.s1 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.380 ns ( 62.60 % ) " "Info: Total cell delay = 0.380 ns ( 62.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.227 ns ( 37.40 % ) " "Info: Total interconnect delay = 0.227 ns ( 37.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.607 ns" { state.s3 Selector1~7 state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.607 ns" { state.s3 {} Selector1~7 {} state.s1 {} } { 0.000ns 0.227ns 0.000ns } { 0.000ns 0.225ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.496 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.618 ns) 2.496 ns state.s1 3 REG LCFF_X39_Y22_N23 2 " "Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk~clkctrl state.s1 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.97 % ) " "Info: Total cell delay = 1.472 ns ( 58.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 41.03 % ) " "Info: Total interconnect delay = 1.024 ns ( 41.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s1 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.496 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.618 ns) 2.496 ns state.s3 3 REG LCFF_X39_Y22_N9 3 " "Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N9; Fanout = 3; REG Node = 'state.s3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk~clkctrl state.s3 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.97 % ) " "Info: Total cell delay = 1.472 ns ( 58.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 41.03 % ) " "Info: Total interconnect delay = 1.024 ns ( 41.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s3 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s1 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s3 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.607 ns" { state.s3 Selector1~7 state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.607 ns" { state.s3 {} Selector1~7 {} state.s1 {} } { 0.000ns 0.227ns 0.000ns } { 0.000ns 0.225ns 0.155ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s1 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s3 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s3 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { state.s1 {} } {  } {  } "" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "state.s1 key clk 2.383 ns register " "Info: tsu for register \"state.s1\" (data pin = \"key\", clock pin = \"clk\") is 2.383 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.789 ns + Longest pin register " "Info: + Longest pin to register delay is 4.789 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns key 1 PIN PIN_J8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_J8; Fanout = 4; PIN Node = 'key'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.508 ns) + CELL(0.346 ns) 4.634 ns Selector1~7 2 COMB LCCOMB_X39_Y22_N22 1 " "Info: 2: + IC(3.508 ns) + CELL(0.346 ns) = 4.634 ns; Loc. = LCCOMB_X39_Y22_N22; Fanout = 1; COMB Node = 'Selector1~7'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.854 ns" { key Selector1~7 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.789 ns state.s1 3 REG LCFF_X39_Y22_N23 2 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.789 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Selector1~7 state.s1 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.281 ns ( 26.75 % ) " "Info: Total cell delay = 1.281 ns ( 26.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.508 ns ( 73.25 % ) " "Info: Total interconnect delay = 3.508 ns ( 73.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.789 ns" { key Selector1~7 state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.789 ns" { key {} key~combout {} Selector1~7 {} state.s1 {} } { 0.000ns 0.000ns 3.508ns 0.000ns } { 0.000ns 0.780ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.496 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.618 ns) 2.496 ns state.s1 3 REG LCFF_X39_Y22_N23 2 " "Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk~clkctrl state.s1 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.97 % ) " "Info: Total cell delay = 1.472 ns ( 58.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 41.03 % ) " "Info: Total interconnect delay = 1.024 ns ( 41.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s1 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.789 ns" { key Selector1~7 state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.789 ns" { key {} key~combout {} Selector1~7 {} state.s1 {} } { 0.000ns 0.000ns 3.508ns 0.000ns } { 0.000ns 0.780ns 0.346ns 0.155ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s1 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s1 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk en state.s0 5.474 ns register " "Info: tco from clock \"clk\" to destination pin \"en\" through register \"state.s0\" is 5.474 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.496 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.618 ns) 2.496 ns state.s0 3 REG LCFF_X39_Y22_N11 3 " "Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk~clkctrl state.s0 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.97 % ) " "Info: Total cell delay = 1.472 ns ( 58.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 41.03 % ) " "Info: Total interconnect delay = 1.024 ns ( 41.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s0 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.884 ns + Longest register pin " "Info: + Longest register to pin delay is 2.884 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state.s0 1 REG LCFF_X39_Y22_N11 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { state.s0 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.154 ns) 0.458 ns en~0 2 COMB LCCOMB_X39_Y22_N28 1 " "Info: 2: + IC(0.304 ns) + CELL(0.154 ns) = 0.458 ns; Loc. = LCCOMB_X39_Y22_N28; Fanout = 1; COMB Node = 'en~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { state.s0 en~0 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.322 ns) + CELL(2.104 ns) 2.884 ns en 3 PIN PIN_J7 0 " "Info: 3: + IC(0.322 ns) + CELL(2.104 ns) = 2.884 ns; Loc. = PIN_J7; Fanout = 0; PIN Node = 'en'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.426 ns" { en~0 en } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.258 ns ( 78.29 % ) " "Info: Total cell delay = 2.258 ns ( 78.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.626 ns ( 21.71 % ) " "Info: Total interconnect delay = 0.626 ns ( 21.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.884 ns" { state.s0 en~0 en } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.884 ns" { state.s0 {} en~0 {} en {} } { 0.000ns 0.304ns 0.322ns } { 0.000ns 0.154ns 2.104ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s0 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.884 ns" { state.s0 en~0 en } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.884 ns" { state.s0 {} en~0 {} en {} } { 0.000ns 0.304ns 0.322ns } { 0.000ns 0.154ns 2.104ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "state.s0 key clk -2.140 ns register " "Info: th for register \"state.s0\" (data pin = \"key\", clock pin = \"clk\") is -2.140 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.496 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 4 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.681 ns) + CELL(0.618 ns) 2.496 ns state.s0 3 REG LCFF_X39_Y22_N11 3 " "Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.299 ns" { clk~clkctrl state.s0 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 58.97 % ) " "Info: Total cell delay = 1.472 ns ( 58.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.024 ns ( 41.03 % ) " "Info: Total interconnect delay = 1.024 ns ( 41.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s0 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.149 ns + " "Info: + Micro hold delay of destination is 0.149 ns" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.785 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.785 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.780 ns) 0.780 ns key 1 PIN PIN_J8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_J8; Fanout = 4; PIN Node = 'key'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { key } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.504 ns) + CELL(0.346 ns) 4.630 ns Selector0~14 2 COMB LCCOMB_X39_Y22_N10 1 " "Info: 2: + IC(3.504 ns) + CELL(0.346 ns) = 4.630 ns; Loc. = LCCOMB_X39_Y22_N10; Fanout = 1; COMB Node = 'Selector0~14'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.850 ns" { key Selector0~14 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 4.785 ns state.s0 3 REG LCFF_X39_Y22_N11 3 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.785 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Selector0~14 state.s0 } "NODE_NAME" } } { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.281 ns ( 26.77 % ) " "Info: Total cell delay = 1.281 ns ( 26.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.504 ns ( 73.23 % ) " "Info: Total interconnect delay = 3.504 ns ( 73.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.785 ns" { key Selector0~14 state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.785 ns" { key {} key~combout {} Selector0~14 {} state.s0 {} } { 0.000ns 0.000ns 3.504ns 0.000ns } { 0.000ns 0.780ns 0.346ns 0.155ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.496 ns" { clk clk~clkctrl state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.496 ns" { clk {} clk~combout {} clk~clkctrl {} state.s0 {} } { 0.000ns 0.000ns 0.343ns 0.681ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.785 ns" { key Selector0~14 state.s0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.785 ns" { key {} key~combout {} Selector0~14 {} state.s0 {} } { 0.000ns 0.000ns 3.504ns 0.000ns } { 0.000ns 0.780ns 0.346ns 0.155ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}