steady_switch.map.qmsg

消除抖动的双稳定开关

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 17 21:12:33 2009 " "Info: Processing started: Tue Mar 17 21:12:33 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off steady_switch -c steady_switch " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off steady_switch -c steady_switch" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "steady_switch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file steady_switch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 steady_switch-art " "Info: Found design unit 1: steady_switch-art" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 steady_switch " "Info: Found entity 1: steady_switch" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "steady_switch " "Info: Elaborating entity \"steady_switch\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|steady_switch\|state 4 " "Info: State machine \"\|steady_switch\|state\" contains 4 states" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|steady_switch\|state " "Info: Selected Auto state machine encoding method for state machine \"\|steady_switch\|state\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|steady_switch\|state " "Info: Encoding result for state machine \"\|steady_switch\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s3 " "Info: Encoded state bit \"state.s3\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s2 " "Info: Encoded state bit \"state.s2\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s1 " "Info: Encoded state bit \"state.s1\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "state.s0 " "Info: Encoded state bit \"state.s0\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|steady_switch\|state.s0 0000 " "Info: State \"\|steady_switch\|state.s0\" uses code string \"0000\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|steady_switch\|state.s1 0011 " "Info: State \"\|steady_switch\|state.s1\" uses code string \"0011\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|steady_switch\|state.s2 0101 " "Info: State \"\|steady_switch\|state.s2\" uses code string \"0101\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|steady_switch\|state.s3 1001 " "Info: State \"\|steady_switch\|state.s3\" uses code string \"1001\"" {  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0 "" 0}  } { { "steady_switch.vhd" "" { Text "E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd" 11 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "8 " "Info: Implemented 8 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "5 " "Info: Implemented 5 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Allocated 152 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 17 21:12:38 2009 " "Info: Processing ended: Tue Mar 17 21:12:38 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}