steady_switch.tan.rpt

消除抖动的双稳定开关

; N/A   ; None         ; 2.383 ns   ; key  ; state.s2 ; clk      ;
; N/A   ; None         ; 2.379 ns   ; key  ; state.s0 ; clk      ;
; N/A   ; None         ; 2.379 ns   ; key  ; state.s3 ; clk      ;
+-------+--------------+------------+------+----------+----------+


+----------------------------------------------------------------+
; tco                                                            ;
+-------+--------------+------------+----------+----+------------+
; Slack ; Required tco ; Actual tco ; From     ; To ; From Clock ;
+-------+--------------+------------+----------+----+------------+
; N/A   ; None         ; 5.474 ns   ; state.s0 ; en ; clk        ;
; N/A   ; None         ; 5.378 ns   ; state.s3 ; en ; clk        ;
+-------+--------------+------------+----------+----+------------+


+----------------------------------------------------------------------+
; th                                                                   ;
+---------------+-------------+-----------+------+----------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To       ; To Clock ;
+---------------+-------------+-----------+------+----------+----------+
; N/A           ; None        ; -2.140 ns ; key  ; state.s0 ; clk      ;
; N/A           ; None        ; -2.140 ns ; key  ; state.s3 ; clk      ;
; N/A           ; None        ; -2.144 ns ; key  ; state.s1 ; clk      ;
; N/A           ; None        ; -2.144 ns ; key  ; state.s2 ; clk      ;
+---------------+-------------+-----------+------+----------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Mar 17 21:13:11 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off steady_switch -c steady_switch --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 500.0 MHz between source register "state.s3" and destination register "state.s1"
    Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.607 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y22_N9; Fanout = 3; REG Node = 'state.s3'
            Info: 2: + IC(0.227 ns) + CELL(0.225 ns) = 0.452 ns; Loc. = LCCOMB_X39_Y22_N22; Fanout = 1; COMB Node = 'Selector1~7'
            Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.607 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'
            Info: Total cell delay = 0.380 ns ( 62.60 % )
            Info: Total interconnect delay = 0.227 ns ( 37.40 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.496 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'
                Info: Total cell delay = 1.472 ns ( 58.97 % )
                Info: Total interconnect delay = 1.024 ns ( 41.03 % )
            Info: - Longest clock path from clock "clk" to source register is 2.496 ns
                Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N9; Fanout = 3; REG Node = 'state.s3'
                Info: Total cell delay = 1.472 ns ( 58.97 % )
                Info: Total interconnect delay = 1.024 ns ( 41.03 % )
        Info: + Micro clock to output delay of source is 0.094 ns
        Info: + Micro setup delay of destination is 0.090 ns
Info: tsu for register "state.s1" (data pin = "key", clock pin = "clk") is 2.383 ns
    Info: + Longest pin to register delay is 4.789 ns
        Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_J8; Fanout = 4; PIN Node = 'key'
        Info: 2: + IC(3.508 ns) + CELL(0.346 ns) = 4.634 ns; Loc. = LCCOMB_X39_Y22_N22; Fanout = 1; COMB Node = 'Selector1~7'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.789 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'
        Info: Total cell delay = 1.281 ns ( 26.75 % )
        Info: Total interconnect delay = 3.508 ns ( 73.25 % )
    Info: + Micro setup delay of destination is 0.090 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.496 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N23; Fanout = 2; REG Node = 'state.s1'
        Info: Total cell delay = 1.472 ns ( 58.97 % )
        Info: Total interconnect delay = 1.024 ns ( 41.03 % )
Info: tco from clock "clk" to destination pin "en" through register "state.s0" is 5.474 ns
    Info: + Longest clock path from clock "clk" to source register is 2.496 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'
        Info: Total cell delay = 1.472 ns ( 58.97 % )
        Info: Total interconnect delay = 1.024 ns ( 41.03 % )
    Info: + Micro clock to output delay of source is 0.094 ns
    Info: + Longest register to pin delay is 2.884 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'
        Info: 2: + IC(0.304 ns) + CELL(0.154 ns) = 0.458 ns; Loc. = LCCOMB_X39_Y22_N28; Fanout = 1; COMB Node = 'en~0'
        Info: 3: + IC(0.322 ns) + CELL(2.104 ns) = 2.884 ns; Loc. = PIN_J7; Fanout = 0; PIN Node = 'en'
        Info: Total cell delay = 2.258 ns ( 78.29 % )
        Info: Total interconnect delay = 0.626 ns ( 21.71 % )
Info: th for register "state.s0" (data pin = "key", clock pin = "clk") is -2.140 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.496 ns
        Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 4; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.681 ns) + CELL(0.618 ns) = 2.496 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'
        Info: Total cell delay = 1.472 ns ( 58.97 % )
        Info: Total interconnect delay = 1.024 ns ( 41.03 % )
    Info: + Micro hold delay of destination is 0.149 ns
    Info: - Shortest pin to register delay is 4.785 ns
        Info: 1: + IC(0.000 ns) + CELL(0.780 ns) = 0.780 ns; Loc. = PIN_J8; Fanout = 4; PIN Node = 'key'
        Info: 2: + IC(3.504 ns) + CELL(0.346 ns) = 4.630 ns; Loc. = LCCOMB_X39_Y22_N10; Fanout = 1; COMB Node = 'Selector0~14'
        Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 4.785 ns; Loc. = LCFF_X39_Y22_N11; Fanout = 3; REG Node = 'state.s0'
        Info: Total cell delay = 1.281 ns ( 26.77 % )
        Info: Total interconnect delay = 3.504 ns ( 73.23 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 114 megabytes of memory during processing
    Info: Processing ended: Tue Mar 17 21:13:12 2009
    Info: Elapsed time: 00:00:01