steady_switch.vhd.bak

消除抖动的双稳定开关

--十六进制可逆计数器同译码器，可在7段数码管显示
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity steady_switch is
port( key,clk: in std_logic;--key为按键输入信号,clk为同步时钟信号
     en:out std_logic);--en为输出控制信号
end;
architecture art of steady_switch is
type state_type is (s0,s1,s2,s3);
signal state: state_type;
begin
process(clk,key)
	 begin
		if rising_edge(clk) then
		  case state is
			when s0=>if(key='1')then state<=s0;
			         else state<=s1;end if;			
			when s1=>if(key='0')then state<=s1;
			         else state<=s2;end if;	
			when s2=>if(key='0')then state<=s3;
			         else state<=s2;end if;			
			when s3=>if(key='0')then state<=s3;
			         else state<=s0;end if;	
			end case;
		 end if;
	 end process;
	en<='0' when(state=s0)or(state=s3) else'1';
end art;