steady_switch.map.rpt

消除抖动的双稳定开关

+-----------------------------------------------------------------------------+--------------------+--------------------+


+-----------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                            ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                               ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------+
; steady_switch.vhd                ; yes             ; User VHDL File  ; E:/2008EDA课本编写/project/steady_switch/steady_switch.vhd ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 5     ;
; Dedicated logic registers                     ; 4     ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 0     ;
;                                               ;       ;
; Total combinational functions                 ; 5     ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 0     ;
;     -- 6 input functions                      ; 0     ;
;     -- 5 input functions                      ; 0     ;
;     -- 4 input functions                      ; 0     ;
;     -- <=3 input functions                    ; 5     ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 5     ;
;     -- extended LUT mode                      ; 0     ;
;     -- arithmetic mode                        ; 0     ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 5     ;
;                                               ;       ;
; Total registers                               ; 4     ;
;     -- Dedicated logic registers              ; 4     ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 3     ;
;                                               ;       ;
; I/O pins                                      ; 3     ;
; Maximum fan-out node                          ; key   ;
; Maximum fan-out                               ; 4     ;
; Total fan-out                                 ; 23    ;
; Average fan-out                               ; 1.92  ;
+-----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                           ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |steady_switch             ; 5 (5)             ; 4 (4)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 3    ; 0            ; |steady_switch      ; work         ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


Encoding Type:  One-Hot
+------------------------------------------------------+
; State Machine - |steady_switch|state                 ;
+----------+----------+----------+----------+----------+
; Name     ; state.s3 ; state.s2 ; state.s1 ; state.s0 ;
+----------+----------+----------+----------+----------+
; state.s0 ; 0        ; 0        ; 0        ; 0        ;
; state.s1 ; 0        ; 0        ; 1        ; 1        ;
; state.s2 ; 0        ; 1        ; 0        ; 1        ;
; state.s3 ; 1        ; 0        ; 0        ; 1        ;
+----------+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 4     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Mar 17 21:12:33 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off steady_switch -c steady_switch
Info: Found 2 design units, including 1 entities, in source file steady_switch.vhd
    Info: Found design unit 1: steady_switch-art
    Info: Found entity 1: steady_switch
Info: Elaborating entity "steady_switch" for the top level hierarchy
Info: State machine "|steady_switch|state" contains 4 states
Info: Selected Auto state machine encoding method for state machine "|steady_switch|state"
Info: Encoding result for state machine "|steady_switch|state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "state.s3"
        Info: Encoded state bit "state.s2"
        Info: Encoded state bit "state.s1"
        Info: Encoded state bit "state.s0"
    Info: State "|steady_switch|state.s0" uses code string "0000"
    Info: State "|steady_switch|state.s1" uses code string "0011"
    Info: State "|steady_switch|state.s2" uses code string "0101"
    Info: State "|steady_switch|state.s3" uses code string "1001"
Info: Implemented 8 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 5 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Allocated 152 megabytes of memory during processing
    Info: Processing ended: Tue Mar 17 21:12:38 2009
    Info: Elapsed time: 00:00:05