tcounter_16b.v.bak

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module test_counter_16b;

reg clk,reset;
wire [3:0] count0,count1,count2,count3;

counter_16b dut(.count0(count0),.count1(count1),.count2(count2),.count3(count3),.clock(clk),.reset(reset));

initial
   begin
	clk=0;
	forever #10 clk=!clk;
   end

initial
   begin
    reset=1;
    #15 reset=0;
    #30 reset=1;
    #10 reset=0;
   end
//initial
   // $monitor($stime,,reset,,clk,,,count);

endmodule