wr_rd.v

高速AD采集卡应用程序及SDRAM控制器

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    16:07:21 01/18/06
// Design Name:    
// Module Name:    sdram_wr_rd
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module wr_rd(clk,sd_data_in,lwr,ads,blast,do_read_ack,do_write_ack,pci_data,do_write,do_read,addr,sd_data_out,sd_rst
//debug
//,next_state
);

input clk;
input lwr;
input ads;
input blast;
input do_read_ack;
input do_write_ack;
input [31:0] sd_data_in;



//output wr_l,rd_l;
output do_write;
output do_read;
output [20:0] addr;
output [31:0] sd_data_out;
output sd_rst;
//debug
//output [3:0]  next_state;



inout	[31:0] pci_data;

//reg wr_l;
//reg rd_l;
reg do_write;
reg do_read;
reg sd_rst;
reg [31:0] sd_data_out; 
reg [31:0] sd_data_in_reg;	
reg [20:0] addr;
reg [31:0] reg_data;
//reg [31:0] previous_data;
reg [3:0]  next_state;
reg [3:0]  read_counter;
reg [2:0]  addrm;
reg [31:0] mem [7:0];
reg [2:0]  rst_counter;

//----------------------------------------------------------------
parameter    idle  = 4'd0,
             reset = 4'd1,  
				// reset_wait = 4'd2,
				 write = 4'd3,
				 write_wait=4'd4,

				 send_read_cmd  = 4'd5,
				 read_wait=4'd6,
				 burst_read=4'd7,
				 read_mem=4'd8;
				
				
				


//---------------------------------------------------------------------------------------------------
assign pci_data=((!lwr)&(!ads))? sd_data_in_reg : 32'hzzzzzzzz;//当pci端发出读信号时，将数据输出，否则呈现高阻，使数据输入


always@(posedge clk)

	begin
		if(lwr&(!blast))     //每当pci写入数据或命令时
			begin
				reg_data<=pci_data;	//	将输入的数据或命令寄存
				//previous_data<=reg_data;		//	与上一次的命令或数据对比
			end
	end
//--------------------------------------------------------------------------
always@(posedge clk)

	begin
		
		case(next_state)
			idle:
				begin
					//wr_l<=1;
					//rd_l<=1;
					do_write<=1'b0;
					do_read<=1'b0;
					sd_rst<=1'b1;
					read_counter<=4'd0;
					rst_counter<=3'd0;
					

					if(lwr&(!blast))		  // 每当pci写入数据或命令时
						next_state<=write;
					//	begin
				
						//	if(pci_data==32'd0)  //	写入全0表示reset sdram,不完善
					//	if(lwr&(!blast)&(pci_data==32'd0))		 
					//if(reg_data==32'd0)

								//begin	
									
															  
					//				next_state<=reset;
					//			end
							//else if(pci_data==32'h7fffeeee)   //写入2147479278发出读命令
						//	else if(lwr&(!blast)&(pci_data==32'h7fffeeee))
					//	else if(reg_data==32'h7fffeeee)
					//			next_state<=send_read_cmd;				
							//else 
					//		else if(lwr&(!blast)&(pci_data!=32'h7fffeeee)&(pci_data!=32'd0))
					//		   next_state<=write;		//其他情况为写入数据
						//end

					else if((!lwr)&(!ads)) 	   	//当pci端发出读信号时
		      				next_state<=read_mem;      //读取寄存器

		        		else next_state<=idle;		//没有读或写表示idle
					
				end
			reset: 
				begin
					sd_rst<=1'b0;
					addr<=21'd0;
					//wr_l<=1;
					//rd_l<=1;
					do_write<=1'b0;
					do_read<=1'b0;
					sd_data_out<=32'd0;

					addrm<=3'd0;
					read_counter<=4'd0;
					mem[0]<=32'd0;
					mem[1]<=32'd0;
					mem[2]<=32'd0;
					mem[3]<=32'd0;
					mem[4]<=32'd0;
					mem[5]<=32'd0;
					mem[6]<=32'd0;
					mem[7]<=32'd0;

					if(rst_counter==3'd5)	 //将rst信号维持低电平的时间维持5个周期
						begin
							rst_counter<=3'd0;
							next_state<=idle;
						end
					else
							begin
								rst_counter<=rst_counter+1;
								next_state<=reset;			
							end  


					//next_state<=reset_wait;
				end

		//	-----------------------------------------------------------
		/*	reset_wait:                              //将reset延长一个时钟周期
				begin
					sd_rst<=0;
               addr<=21'd0;
					//wr_l<=1;
					//rd_l<=1;
					do_write<=0;
					do_read<=0;
					sd_data_out<=32'd0;

					addrm<=3'd0;
					read_counter<=4'd0;
					mem[0]<=32'd0;
					mem[1]<=32'd0;
					mem[2]<=32'd0;
					mem[3]<=32'd0;
					mem[4]<=32'd0;
					mem[5]<=32'd0;
					mem[6]<=32'd0;
					mem[7]<=32'd0;

					
					next_state<=idle;
				end
				*/
				//---------------------------------------------------------------------------

			write:                                       //可能要加入等待周期
				begin
					sd_rst<=1'b1;
					
					if(reg_data==32'd0)
						begin
							sd_rst<=1'b0;
							next_state<=reset;
						end
					else if(reg_data==32'h7fffeeee)   //写入2147479278发出读命令
						next_state<=send_read_cmd;
					else
						begin	
							//wr_l<=0;							  //发出写命令
							do_write<=1'b1;						  //发出写命令
							sd_data_out<=reg_data;		//向sdram发出数据

							if(addr==21'd7)						 //发出地址
								addr<=21'd0;
							else addr<=addr+1;

							next_state<=write_wait;
						end
				end
			write_wait:
				begin
					sd_rst<=1'b1;
					//调试屏蔽wr_l<=1;			  //不需要一直为低

					sd_data_out<=sd_data_out; //保持输出数据不变
					//addr<=addr;		//保持地址不变

					if(do_write_ack)	  
						begin		  							
							//wr_l<=1;
							do_write<=1'b0;
							next_state<=idle;
						end
					else next_state<=write_wait;


				end

			

			send_read_cmd:                                         //可能要加入等待周期
				begin
					sd_rst<=1'b1;
					//rd_l<=0;        //send read command
					do_read<=1'b1;			//send read command

					addr<=21'd0;     //给出猝发读的初始地址

					//if(addr==7)
					  //addr<=21'd0;
					//else addr<=addr+1;

					//sd_data_in_reg<=sd_data_in;

					//next_state<=idle;
					next_state<=read_wait;
				end
			read_wait:                                    //等待数据有效
				begin
					sd_rst<=1;
					//调试屏蔽 rd_l<=1;  //不需要一直为低		 
					//addr<=addr;//地址保持
					
					if(do_read_ack)   //当收到do_read_ack后表示下一个周期数据有效，开始接受数据
						begin
							//rd_l<=1;
							do_read<=1'b0;	
							next_state<=burst_read;
						end		 
					else next_state<=read_wait;
				end
			burst_read:                                 //将sdram的数据写道存储器mem中
				begin
					sd_rst<=1'b1;
					//rd_l<=1;
					do_read<=1'b0;
				
				
					if(addrm==3'd7)
						addrm<=3'd0;
					else 
						begin
							addrm<=addrm+1;					
							mem[addrm]<=sd_data_in;
						end
			
					
					if(read_counter==4'd8)
						begin
							read_counter<=1'b0;
                     next_state<=idle;
							
						end
					else 
						begin
							read_counter<=read_counter+1;
							next_state<=burst_read;
						end
					
				end

			read_mem:

				begin
					sd_rst<=1'b1;
					//rd_l<=1;
					do_read<=1'b0;
					if(addrm==3'd7)
						addrm<=3'd0;
					else
						begin
							addrm<=addrm+1;
							sd_data_in_reg<=mem[addrm];   //sd_data_in_reg是pci_data的输出寄存器

						end
					next_state<=idle;	

				end
			
			default:next_state<=idle;

		endcase
	end


endmodule