hostcont.v

高速AD采集卡应用程序及SDRAM控制器

// MP ADDRESS LATCH
// Transparent latch
// Used to hold the addx from the micro. Latch on the falling edge of
// do_write.
// BAsed on the way "do_write" is generated, we only need to latch on the writes
// since the write can be queued, but since all reads are blocked, the latch
// will not latch the addx on reads.  


//先屏蔽assign reg_mp_addx = mp_addx;


//-----------------------------------------------------------------------------------------------------


// MP DATA LATCH
// Used to hold the data from the micro.  Latch on the rising edge
// of mp_wr_l

//always @(mp_data_in)
 //    reg_mp_data <= mp_data_in;

 /*
 always @(posedge sys_clk or negedge sys_rst_l)
	 begin
	 	if(~sys_rst_l)
		sd_data_out<=31'h00000000;
		else
		sd_data_out<=mp_data_in;
	 end
 */

//-----------------------------------------------------------------------------------------------------------------------------

//
// MODE REG REG
//
//`define default_mode_reg {4'b0000,`default_mode_reg_CAS_LATENCY,`defulat_mode_reg_BURST_TYPE,`default_mode_reg_BURST_LENGHT}  //配置寄存器的值
//`define default_mode_reg 11'b01000100000
//reg_modeset的作用是存储配置寄存器的信息
//调试屏蔽
 /*
always @(posedge sys_clk or negedge sys_rst_l)
begin
    if (~sys_rst_l)
        reg_modeset <= 11'd0;
    else  if (pwrup)	
        //reg_modeset <= `default_mode_reg;
         // reg_modeset<=11'd528;	 
			                                 //这里设为猝发长度为1，
			                                 //	caslatency=1,单次写入
			
		 		reg_modeset<=11'b01000010011;//	 这里设为读猝发长度为8，caslatency=1,单次写入
	  else reg_modeset<=	11'd0;
    //else 
    //if (~sdram_mode_set_l & ~mp_cs_l & ~mp_wr_l)
        //reg_modeset <= mp_data_in[10:0];//////？？？作用不明
end
*/
//-------------------------------------------------------------------------------------------------------------------------------------

// SD DATA REGISTER
// This register holds in the data from the SDRAM
//
/*
always @(posedge sys_clk or negedge sys_rst_l)
  if (~sys_rst_l)
 //   reg_sd_data <= 32'h00000000;
      mp_data_out<=32'd0;
  else if (sd_rd_ena)
    //reg_sd_data <= sd_data_buff; //sd_data_buff是wire类型的
	 //reg_sd_data<=sd_data_in;
	 	mp_data_out<=sd_data_in;
		*/


//
// SD DATA BUS BUFFERS
//
//调试屏蔽assign sd_data_out  = reg_mp_data;
//assign sd_data_buff = sd_data_in;

//-----------------------------------------------------------------------------------------------------------------

// SDRAM SIDE ADDX
/*
// SD_BA
always @(sd_addx_mux or reg_mp_addx)
  case (sd_addx_mux)
    2'b00:    sd_ba <= reg_mp_addx[20:19];     //给出bank地址
    2'b01:    sd_ba <= reg_mp_addx[20:19];     //给出bank地址
    default:  sd_ba <= 2'b00;
  endcase

//SD地址的第10位
always @(sd_addx10_mux or reg_mp_data or reg_mp_addx or reg_modeset)
  case (sd_addx10_mux)
    2'b00:   sd_addx[10] <= reg_mp_addx[18];//row
    2'b01:   sd_addx[10] <= 1'b0;           //column，因为列地址只有8bit，所以此时sd_addx[10] 输出0，

    2'b10:   sd_addx[10] <= reg_modeset[10];
    default: sd_addx[10] <= 1'b1;
  endcase

//SD地址的0—9位

always @(sd_addx_mux or reg_modeset or reg_mp_addx)
  case (sd_addx_mux)
    2'b00:   sd_addx[9:0] <= reg_mp_addx[17:8];               // ROW
    2'b01:   sd_addx[9:0] <= {2'b00, reg_mp_addx[7:0]};        // 全0
    2'b10:   sd_addx[9:0] <= reg_modeset[9:0];
    default: sd_addx[9:0] <= 10'h000;
  endcase
*/
//---------------------------------------------------------------------------------------------
// SD_BA
always @(sd_addx_mux or mp_addx)
  case (sd_addx_mux)
    2'b00:    sd_ba <=  mp_addx[20:19];     //bank address
    2'b01:    sd_ba <=  mp_addx[20:19];     //bank address
    default:  sd_ba <= 2'b00;
  endcase

//SD地址的第10位
always @(sd_addx10_mux  or mp_addx)
  case (sd_addx10_mux)
    2'b00:   sd_addx[10] <= mp_addx[18];//row
    2'b01:   sd_addx[10] <= 1'b0;           //column，因为列地址只有8bit，所以此时sd_addx[10] 输出0，

    2'b10:   sd_addx[10] <= 1'b0;
    default: sd_addx[10] <= 1'b1;			  //	precharge all banks
  endcase

//SD地址的0—9位

always @(sd_addx_mux or mp_addx )
  case (sd_addx_mux)
    2'b00:   sd_addx[9:0] <= mp_addx[17:8];               // ROW
    2'b01:   sd_addx[9:0] <= {2'b00, mp_addx[7:0]};        // COLUMN
    //2'b10:   sd_addx[9:0] <= reg_modeset[9:0];
	 
	  2'b10:   sd_addx[9:0] <=   10'b0000110111;	//设置为caslatency=3,全页猝发读写

	 default: sd_addx[9:0] <= 10'h000;
  endcase

//-----------------------------------------------------------------------------------------------------------------------

// Micro data mux
//assign reg_mp_data_mux = mp_data_mux ? 32'h00000000 : reg_mp_data;  ////？

// MP_DATA_OUT mux
//always @(reg_sd_data)
 // mp_data_out <= reg_sd_data;


//-----------------------------------------------------------------------------------------------------------------------------------

//
// DO_READ   DO_WRITE   
// signal generation
//

/*

always @(posedge sys_clk or negedge sys_rst_l)
begin
  if (~sys_rst_l) begin
    do_read  <= `LO;
    do_write <= `LO;
    //do_modeset <= `LO;////////？？？？？
    do_state <= 3'b000;
    busy_a_ena <= `HI; 
  end
  else 
    case (do_state)
        // hang in here until a read or write is requested 
        // (mp_rd_l = 1'b0) or (mp_wr_l = 1'b0)
        3'b000: 
		  begin
            // a read request
            //if (~mp_rd_l & ~mp_cs_l) begin 
		   	if(~mp_rd_l)   
				  begin    
                do_read <= `HI;
                do_state <= 3'b001;
            	end
            // a write request           
				else if(~mp_wr_l) 
					begin   
                do_write <= `HI;
                do_state <= 3'b001;
            	end  
				else do_state<=3'b000;
				          
        end	         
        // This cycle is dummy cycle.  Just to extend 'busy_ena_a' 
        // to a total of 2 cycles 
        3'b001:
            begin
                busy_a_ena <= `LO;      // disable busy_a generation
                if (do_write)
                   do_state <= 3'b011;
                else if (do_read)
                   do_state <= 3'b010;
              
                else 
                   do_state <= 3'b001;
            end

        // hang in here until the sdramcnt has acknowledged the
        // read
        3'b010:
		  		begin
            	if (do_read_ack)
					 begin
                	do_read <= `LO;
                	do_state <= 3'b100;
            		end
            	else
                do_state <= 3'b010;
				end

        // hang in here until the sdramcnt has acknowledged the 
        // write
        3'b011:
		  	begin
            if (do_write_ack)
				  begin
                 do_write <= `LO;
                 do_state <= 3'b101;
              end
            else
                do_state <= 3'b011;
			end

        // wait in here until the host has read the data
        // (i.e. has raised its mp_rd_l high)
        3'b100:
		      begin
              if (mp_rd_l) 
				  		begin
                  	busy_a_ena <= `HI;      // re-enable busy_a generation
                  	do_state <= 3'b000;
                 	end
              else
                do_state <= 3'b100;
				end

                
        // wait in here until the host has relinquieshed the write bus
        // (i.e. has raised its mp_wr_l high)
        3'b101:
		    begin
             if (mp_wr_l)
				 	 begin
               	 busy_a_ena <= `HI;      // re-enable busy_a generation
                	 do_state <= 3'b000;
            	end
            else
                do_state <= 3'b101;
			end   
		 default: do_state<=3'b000;  


    endcase
end
*/
                



endmodule