databuf.v

高速AD采集卡应用程序及SDRAM控制器

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    13:32:30 10/22/06
// Design Name:    
// Module Name:    databuf
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module databuf(clk200m,clk100m,datain,dataout,rst
					//DEBUG
					//,datareg1,datadly,datareg2
					);
input rst;	
input clk200m;
input clk100m;
//input[7:0] datain;
input[15:0] datain;
//output [15:0] dataout;
output [31:0] dataout;
//DEBUG
//output [7:0] datareg1,datadly,datareg2;

reg counter;
//reg [7:0] datareg,datareg1,datareg2,datadly;
reg [15:0] datareg,datareg1,datareg2,datadly;
//reg [7:0] data1,data2;
reg [15:0] data1,data2;
//reg [15:0] dataout;
reg [31:0] dataout;
//reg [15:0] dataoutreg;

always@(posedge clk200m or negedge rst)
begin	
		if(!rst)
			counter<=1'b0;
		else
	  		counter<=~counter;
end

always@(posedge clk200m or negedge rst)	 
begin	
		if(!rst)					 //异步复位
			//datareg<=8'd0;
			datareg<=16'd0;
		else
	  		datareg<=datain;		  //把输入的数据存起来
end

always@(posedge clk200m or negedge rst)
 begin
 	if(!rst)						//异步复位
		begin
			 //datareg1<=8'd0;
			 //datareg2<=8'd0;
			 datareg1<=16'd0;
			 datareg2<=16'd0;
		end
		else
			begin
				case(counter)
					0:datareg1<=datareg;
					1:datareg2<=datareg;
				endcase
			end
end

always@(posedge clk200m or negedge rst)
 begin
 	if(!rst)					 //异步复位
      //datadly<=8'd0;
			datadly<=16'd0;
	else
		datadly<=datareg1;
end

always@(posedge clk100m or negedge rst)	  //这里clk100m已经经过了DCM模块180度的相位延时，所以使用上升沿
//always@(negedge clk100m)
begin

 	if(!rst)					  //异步复位
   //   dataout<=16'd0;
	  begin
		  //data1<=8'd0;
		  //data2<=8'd0;
        //dataout<=16'd0;

		  data1<=16'd0;
		  data2<=16'd0;
        dataout<=32'd0;
	  end
   else
		  begin
          data1<=	datadly;
          data2<= datareg2;
			 dataout<={data1[15:0],data2[15:0]};

//dataout<={datadly[7:0],datareg2[7:0]};
          //dataout<={data1[7:0],data2[7:0]};
			//	dataoutreg<={datadly[7:0],datareg2[7:0]};
			//	dataout<=dataoutreg;
			end

 end

endmodule