📄 counter.rpt
字号:
& = Uses single-pin Output Enable
Device-Specific Information:f:\max2work\xiongbin\useful\cepincemaikuan\counter.rpt
counter
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - A 21 AND2 0 3 0 1 |LPM_ADD_SUB:314|addcore:adder|:171
- 6 - A 21 AND2 0 4 0 3 |LPM_ADD_SUB:314|addcore:adder|:175
- 3 - A 17 AND2 0 3 0 4 |LPM_ADD_SUB:314|addcore:adder|:183
- 7 - A 19 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:187
- 6 - A 19 AND2 0 4 0 2 |LPM_ADD_SUB:314|addcore:adder|:195
- 2 - A 19 AND2 0 2 0 4 |LPM_ADD_SUB:314|addcore:adder|:199
- 7 - A 20 AND2 0 3 0 1 |LPM_ADD_SUB:314|addcore:adder|:207
- 1 - A 20 AND2 0 4 0 4 |LPM_ADD_SUB:314|addcore:adder|:211
- 6 - A 24 AND2 0 3 0 1 |LPM_ADD_SUB:314|addcore:adder|:219
- 8 - A 24 AND2 0 4 0 4 |LPM_ADD_SUB:314|addcore:adder|:223
- 7 - A 14 AND2 0 3 0 1 |LPM_ADD_SUB:314|addcore:adder|:231
- 2 - A 14 AND2 0 4 0 4 |LPM_ADD_SUB:314|addcore:adder|:235
- 3 - A 16 AND2 0 3 0 1 |LPM_ADD_SUB:314|addcore:adder|:243
- 1 - A 16 AND2 0 4 0 3 |LPM_ADD_SUB:314|addcore:adder|:247
- 2 - A 16 AND2 0 3 0 4 |LPM_ADD_SUB:314|addcore:adder|:255
- 7 - A 15 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:259
- 1 - A 15 AND2 0 4 0 4 |LPM_ADD_SUB:314|addcore:adder|:267
- 5 - A 23 AND2 0 2 0 1 |LPM_ADD_SUB:314|addcore:adder|:271
- 3 - A 23 AND2 0 4 0 2 |LPM_ADD_SUB:314|addcore:adder|:279
- 1 - A 04 AND2 0 3 0 3 |LPM_ADD_SUB:935|addcore:adder|:171
- 1 - A 08 AND2 0 3 0 4 |LPM_ADD_SUB:935|addcore:adder|:179
- 3 - A 08 AND2 0 3 0 1 |LPM_ADD_SUB:935|addcore:adder|:187
- 2 - A 08 AND2 0 4 0 4 |LPM_ADD_SUB:935|addcore:adder|:191
- 7 - A 07 AND2 0 3 0 1 |LPM_ADD_SUB:935|addcore:adder|:199
- 1 - A 07 AND2 0 4 0 4 |LPM_ADD_SUB:935|addcore:adder|:203
- 2 - A 10 AND2 0 3 0 1 |LPM_ADD_SUB:935|addcore:adder|:211
- 5 - A 10 AND2 0 4 0 4 |LPM_ADD_SUB:935|addcore:adder|:215
- 7 - A 10 AND2 0 3 0 1 |LPM_ADD_SUB:935|addcore:adder|:223
- 8 - A 10 AND2 0 4 0 4 |LPM_ADD_SUB:935|addcore:adder|:227
- 7 - A 06 AND2 0 3 0 1 |LPM_ADD_SUB:935|addcore:adder|:235
- 1 - A 06 AND2 0 4 0 3 |LPM_ADD_SUB:935|addcore:adder|:239
- 2 - A 06 AND2 0 3 0 3 |LPM_ADD_SUB:935|addcore:adder|:247
- 1 - A 01 AND2 0 3 0 4 |LPM_ADD_SUB:935|addcore:adder|:255
- 5 - A 11 AND2 0 2 0 1 |LPM_ADD_SUB:935|addcore:adder|:259
- 7 - A 11 AND2 0 4 0 4 |LPM_ADD_SUB:935|addcore:adder|:267
- 3 - A 03 AND2 0 2 0 1 |LPM_ADD_SUB:935|addcore:adder|:271
- 4 - A 03 AND2 0 4 0 2 |LPM_ADD_SUB:935|addcore:adder|:279
- 4 - A 05 DFFE 1 3 0 1 BZQ31 (:18)
- 3 - A 05 DFFE 1 2 0 2 BZQ30 (:19)
- 7 - A 23 DFFE 1 3 0 2 BZQ29 (:20)
- 4 - A 23 DFFE 1 3 0 3 BZQ28 (:21)
- 1 - A 23 DFFE 1 2 0 4 BZQ27 (:22)
- 8 - A 15 DFFE 1 3 0 2 BZQ26 (:23)
- 6 - A 15 DFFE 1 3 0 3 BZQ25 (:24)
- 5 - A 15 DFFE 1 2 0 4 BZQ24 (:25)
- 5 - A 16 DFFE 1 3 0 2 BZQ23 (:26)
- 6 - A 16 DFFE 1 2 0 3 BZQ22 (:27)
- 4 - A 16 DFFE 1 2 0 2 BZQ21 (:28)
- 8 - A 16 DFFE 1 3 0 3 BZQ20 (:29)
- 7 - A 16 DFFE 1 2 0 4 BZQ19 (:30)
- 8 - A 14 DFFE 1 2 0 2 BZQ18 (:31)
- 4 - A 14 DFFE 1 3 0 3 BZQ17 (:32)
- 3 - A 14 DFFE 1 2 0 4 BZQ16 (:33)
- 7 - A 24 DFFE 1 2 0 2 BZQ15 (:34)
- 5 - A 24 DFFE 1 3 0 3 BZQ14 (:35)
- 4 - A 24 DFFE 1 2 0 4 BZQ13 (:36)
- 8 - A 20 DFFE 1 2 0 2 BZQ12 (:37)
- 6 - A 20 DFFE 1 3 0 3 BZQ11 (:38)
- 5 - A 20 DFFE 1 2 0 4 BZQ10 (:39)
- 8 - A 19 DFFE 1 2 0 2 BZQ9 (:40)
- 3 - A 19 DFFE 1 3 0 2 BZQ8 (:41)
- 1 - A 19 DFFE 1 3 0 3 BZQ7 (:42)
- 4 - A 19 DFFE 1 2 0 4 BZQ6 (:43)
- 5 - A 17 DFFE 1 3 0 2 BZQ5 (:44)
- 2 - A 17 DFFE 1 2 0 3 BZQ4 (:45)
- 7 - A 21 DFFE 1 2 0 2 BZQ3 (:46)
- 2 - A 21 DFFE 1 3 0 3 BZQ2 (:47)
- 1 - A 21 DFFE 1 2 0 4 BZQ1 (:48)
- 8 - A 12 DFFE 1 1 0 5 BZQ0 (:49)
- 3 - B 12 DFFE + 0 0 0 32 BCLK (:50)
- 6 - A 01 DFFE + 0 3 0 1 TSQ31 (:51)
- 2 - A 01 DFFE + 0 2 0 2 TSQ30 (:52)
- 6 - A 03 DFFE + 0 3 0 2 TSQ29 (:53)
- 2 - A 03 DFFE + 0 3 0 3 TSQ28 (:54)
- 1 - A 03 DFFE + 0 2 0 4 TSQ27 (:55)
- 6 - A 11 DFFE + 0 3 0 2 TSQ26 (:56)
- 4 - A 11 DFFE + 0 3 0 3 TSQ25 (:57)
- 3 - A 11 DFFE + 0 2 0 4 TSQ24 (:58)
- 5 - A 01 DFFE + 0 3 0 2 TSQ23 (:59)
- 3 - A 01 DFFE + 0 2 0 3 TSQ22 (:60)
- 5 - A 06 DFFE + 0 3 0 2 TSQ21 (:61)
- 8 - A 06 DFFE + 0 2 0 3 TSQ20 (:62)
- 3 - A 06 DFFE + 0 2 0 2 TSQ19 (:63)
- 6 - A 06 DFFE + 0 3 0 3 TSQ18 (:64)
- 4 - A 06 DFFE + 0 2 0 4 TSQ17 (:65)
- 3 - A 10 DFFE + 0 2 0 2 TSQ16 (:66)
- 6 - A 10 DFFE + 0 3 0 3 TSQ15 (:67)
- 1 - A 10 DFFE + 0 2 0 4 TSQ14 (:68)
- 1 - A 02 DFFE + 0 2 0 2 TSQ13 (:69)
- 4 - A 10 DFFE + 0 3 0 3 TSQ12 (:70)
- 5 - A 12 DFFE + 0 2 0 4 TSQ11 (:71)
- 8 - A 07 DFFE + 0 2 0 2 TSQ10 (:72)
- 6 - A 07 DFFE + 0 3 0 3 TSQ9 (:73)
- 5 - A 07 DFFE + 0 2 0 4 TSQ8 (:74)
- 5 - A 08 DFFE + 0 2 0 2 TSQ7 (:75)
- 7 - A 08 DFFE + 0 3 0 3 TSQ6 (:76)
- 6 - A 08 DFFE + 0 2 0 4 TSQ5 (:77)
- 8 - A 08 DFFE + 0 3 0 2 TSQ4 (:78)
- 4 - A 08 DFFE + 0 2 0 3 TSQ3 (:79)
- 7 - A 04 DFFE + 0 3 0 2 TSQ2 (:80)
- 6 - A 04 DFFE + 0 2 0 3 TSQ1 (:81)
- 5 - A 04 DFFE + 0 1 0 4 TSQ0 (:82)
- 2 - C 14 DFFE + 1 0 1 32 ENA (:83)
- 6 - A 09 AND2 3 0 0 8 :1368
- 8 - A 09 AND2 3 0 0 8 :1372
- 7 - A 09 AND2 3 0 0 8 :1376
- 4 - A 09 AND2 3 0 0 8 :1380
- 1 - A 09 AND2 3 0 0 8 :1384
- 2 - A 09 OR2 ! 3 0 0 8 :1388
- 5 - A 09 AND2 3 0 0 8 :1392
- 8 - A 01 OR2 0 3 0 1 :1559
- 2 - C 06 OR2 0 3 0 1 :1565
- 7 - A 05 OR2 0 3 0 1 :1571
- 8 - A 05 OR2 0 3 0 1 :1577
- 2 - A 05 OR2 0 3 0 1 :1583
- 1 - A 24 OR2 0 3 0 1 :1589
- 4 - A 17 OR2 0 3 1 0 :1595
- 7 - A 01 OR2 0 3 0 1 :1604
- 4 - A 01 OR2 0 3 0 1 :1607
- 5 - A 05 OR2 0 3 0 1 :1610
- 6 - A 05 OR2 0 3 0 1 :1613
- 1 - A 05 OR2 0 3 0 1 :1616
- 2 - A 24 OR2 0 3 0 1 :1619
- 8 - A 17 OR2 0 3 1 0 :1622
- 5 - A 03 OR2 0 3 0 1 :1631
- 4 - A 02 OR2 0 3 0 1 :1634
- 8 - A 02 OR2 0 3 0 1 :1637
- 2 - A 23 OR2 0 3 0 1 :1640
- 1 - A 13 OR2 0 3 0 1 :1643
- 3 - A 24 OR2 0 3 0 1 :1646
- 1 - A 17 OR2 0 3 1 0 :1649
- 8 - A 03 OR2 0 3 0 1 :1658
- 2 - A 02 OR2 0 3 0 1 :1661
- 3 - A 02 OR2 0 3 0 1 :1664
- 8 - A 23 OR2 0 3 0 1 :1667
- 2 - A 22 OR2 0 3 0 1 :1670
- 4 - A 20 OR2 0 3 0 1 :1673
- 7 - A 17 OR2 0 3 1 0 :1676
- 7 - A 03 OR2 0 3 0 1 :1685
- 3 - A 12 OR2 0 3 0 1 :1688
- 6 - A 12 OR2 0 3 0 1 :1691
- 6 - A 23 OR2 0 3 0 1 :1694
- 6 - A 18 OR2 0 3 0 1 :1697
- 3 - A 20 OR2 0 3 0 1 :1700
- 5 - A 21 OR2 0 3 1 0 :1703
- 8 - A 11 OR2 0 3 0 1 :1712
- 3 - A 07 OR2 0 3 0 1 :1715
- 2 - A 04 OR2 0 3 0 1 :1718
- 3 - A 15 OR2 0 3 0 1 :1721
- 1 - A 14 OR2 0 3 0 1 :1724
- 2 - A 20 OR2 0 3 0 1 :1727
- 3 - A 21 OR2 0 3 1 0 :1730
- 1 - A 11 OR2 0 3 0 1 :1739
- 2 - A 07 OR2 0 3 0 1 :1742
- 4 - A 04 OR2 0 3 0 1 :1745
- 4 - A 15 OR2 0 3 0 1 :1748
- 5 - A 14 OR2 0 3 0 1 :1751
- 5 - A 19 OR2 0 3 0 1 :1754
- 8 - A 21 OR2 0 3 1 0 :1757
- 2 - A 11 OR2 0 3 0 1 :1766
- 4 - A 07 OR2 0 3 0 1 :1769
- 3 - A 04 OR2 0 3 0 1 :1772
- 2 - A 15 OR2 0 3 0 1 :1775
- 6 - A 14 OR2 0 3 0 1 :1778
- 2 - A 12 OR2 0 3 0 1 :1781
- 1 - A 12 OR2 0 3 1 0 :1784
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:f:\max2work\xiongbin\useful\cepincemaikuan\counter.rpt
counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 36/ 96( 37%) 32/ 48( 66%) 32/ 48( 66%) 2/16( 12%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:f:\max2work\xiongbin\useful\cepincemaikuan\counter.rpt
counter
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 33 TCLK
DFF 33 BCLK
INPUT 1 CLKB
Device-Specific Information:f:\max2work\xiongbin\useful\cepincemaikuan\counter.rpt
counter
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 65 CLR
Device-Specific Information:f:\max2work\xiongbin\useful\cepincemaikuan\counter.rpt
counter
** EQUATIONS **
BENA : INPUT;
CL : INPUT;
CLKB : INPUT;
CLR : INPUT;
SEL0 : INPUT;
SEL1 : INPUT;
SEL2 : INPUT;
TCLK : INPUT;
-- Node name is ':50' = 'BCLK'
-- Equation name is 'BCLK', location is LC3_B12, type is buried.
BCLK = DFFE(!BCLK, GLOBAL( CLKB), VCC, VCC, VCC);
-- Node name is ':49' = 'BZQ0'
-- Equation name is 'BZQ0', location is LC8_A12, type is buried.
BZQ0 = DFFE( _EQ001, BCLK, GLOBAL(!CLR), VCC, VCC);
_EQ001 = !BENA & BZQ0
# BENA & !BZQ0;
-- Node name is ':48' = 'BZQ1'
-- Equation name is 'BZQ1', location is LC1_A21, type is buried.
BZQ1 = DFFE( _EQ002, BCLK, GLOBAL(!CLR), VCC, VCC);
_EQ002 = !BZQ0 & BZQ1
# BENA & BZQ0 & !BZQ1
# !BENA & BZQ1;
-- Node name is ':47' = 'BZQ2'
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